JPH02230831A - Synchronization detecting circuit - Google Patents

Abstract

PURPOSE:To attain the establishment of synchronization of plural parallel data by setting a condition with a condition setting means so that the replacement of N-set of parallel data patterns at a channel replacement section is implemented at the 1st stage of backward protection with a protection means, when the protecting means executes the protecting processing in order to establish the synchronization. CONSTITUTION:A coincidence pulse outputted based on a data pattern detected with a pattern detecting section 1 is latched by a latch means 20 and the synchronization protection of a parallel data is taken based on the coincidence pulse selected sequentially at one protecting means 30 depending on the latch output. Then a control signal to replace N-set of parallel data patterns at the timing of the 1st stage of backward protection by one protection means 30 is outputted to a channel replacement section 5. The output condition of the control signal to replace the N-set of parallel data patterns at the channel replacement section 5 at the 1st stage of the backward protection in the protection means 30 is set and outputted by a condition setting means 60. Thus, the replacement of the parallel data is efficiently attained.

Description

[Detailed Description of the Invention] [Summary] Regarding a synchronization detection circuit that establishes frame synchronization after separating a high-order group signal into N parallel signals, it is possible to efficiently establish synchronization of multiple parallel data with a simple circuit configuration. The purpose is to provide a synchronization detection circuit that can detect N parallel data in which the arrangement of data bits is different.
Among the N types of matching pulses detected and output by the pattern detection unit from the regular frame patterns, the frame pattern that is not latched by the latch means is considered out of synchronization, and the protection means performs protection processing to establish the same #J1. The condition setting means is configured to set a condition so that the protection means performs switching in the channel switching section of the N parallel data patterns when the protection processing for establishing synchronization is performed by the means in the first stage of backward protection. do.

[Industrial application field]

The present invention relates to a synchronization detection circuit that establishes frame synchronization after separating a high-order group signal into N parallel signals.

To establish frame synchronization of N parallel data, N
Detects N possible frame patterns based on combinations of data bit order from parallel data,
Generally, N synchronization protection circuits are provided to protect each of the N frame patterns.
Therefore, as the number of parallel data increases, the number of synchronization protection circuits increases proportionally.

On the other hand, if N parallel data is asynchronous, the pattern order is undefined, so it is necessary to rearrange it into a synchronous state after establishing synchronization, but this rearrangement is usually done when synchronization is established during backward protection. It is done after that. Therefore, the synchronization processing time depends on the number of stages of backward protection.

As circuit scale becomes smaller and high-speed processing is desired, it is desired to realize a synchronization detection circuit that eliminates these problems.

[Conventional technology]

Figure 3 is a diagram explaining a conventional example of a synchronization detection circuit, Figure 4 is a diagram explaining an example of how the synchronization detection circuit is used, and Figure 5 is a diagram explaining an example of separating serial data into parallel data. .

A conventional synchronization detection circuit (hereinafter referred to as FSYNC) 300 shown in FIG. 3 includes a pattern detection section 1, a synchronization protection section 3. Timing creation unit 4 and channel (hereinafter abbreviated as CH)
The above-mentioned pattern detection section 1 performs synchronous monitoring of parallel data bits in order to detect a data pattern after being separated in parallel, and has (n+1) bits of parallel data. Flip-flop circuits (hereinafter referred to as F, F circuits) 1 to F, F circuits n+1 are connected in series, and this F. A number of series F circuits are arranged in parallel according to the number of parallel data.

Incidentally, F. of the pattern detection section 1 shown in FIG. F circuit 1
~F, F circuit n+1 shows one representative column.

Next, F. F circuit 1 to F, F circuit n+
The device is equipped with n gate circuits G1 to Gn for extracting a matching pulse output when all of the data patterns among the N data pattern outputs match in synchronization bits.

Further, the synchronization protection unit 3 includes n synchronization protection circuits #l to synchronization protection for establishing synchronization protection of N parallel data using N coincidence pulses taken out from n gate circuits G1 to Gn. It is equipped with a circuit #n and a gate circuit 33 for gating the n outputs of the synchronization protection section 3, and the timing generation section 4 has a logic that takes the logical sum of the outputs from the n gate circuits G1 to On. A sum circuit (hereinafter referred to as an OR circuit) 41 and a frame counter 4 that counts a clock CLK output from a clock generator (not shown) or the like.
2, a mismatch detection circuit 43 that detects coincidence/mismatch between the output of the OR circuit 41 and the output of the frame counter 42;
Output of gate circuit 33 in synchronization protection section 3 and clock CLK
An AND circuit (hereinafter referred to as an AND circuit) that ANDs the
44.

Note that the number N of parallel data mentioned above is N=
In this case, it is set to 8.

FIG. 4 shows a configuration in which FSYNC300 is used as part of a high-speed module.

That is, the FSFNC300 is one of the high-speed modules that converts multiplexed serial data transmitted through an optical cable (a) into parallel data, synchronizes the data, and separates the multiplexed data into a plurality of parallel data. The configuration includes an O/E converter 100 that converts an optical signal transmitted via an optical cable (a) into an electrical signal, and a serial data converter 100 that converts an optical signal into an electrical signal. For example, an S/P converter 200 that converts into 8 columns of parallel data and an FSFNC 3 shown in FIG.
00, a DSRB 400 that descrambles scrambled data, and a DMUX 500 that separates multiplexed 8-column parallel data into three 8-column parallel data.

Next, FIG. 5 shows an example in which parallel data input to FSYNC300 is separated from serial data.
Figure (A) shows the format of serial data input to the S/P converter 200, and symbols A to H in the figure represent data bits, each consisting of one bit.

This serial data is processed by the S/P converter 200 as shown in FIG.
As shown in B), it is converted into eight columns of parallel data and sent to the FSFNC 300 as one pattern.

FIG. 5(B) (1) to (3) are examples when converted to an 8-column parallel data pattern, and symbols (C) to [Yes]
)" indicates each phase point when converted into an 8-column parallel data pattern.

For example, at the phase point (b), the A data bit is sequentially converted into H data bits and 8 columns of parallel data, and this is an example of a normal data pattern.

Also, at the (b)' phase point, the A data bit is in the 8th column, and the 1st column of the next phase is the B data bit, and the 2nd column is C.
This is an example of a data pattern that continues with data bits, and the phase point is data where the 7th column is the A data bit, the B data bit is in the 8th column, and the 1st column of the next phase is the C data bit. This is an example of a pattern.

The FSFNC 300 establishes data synchronization by detecting the case where all eight columns of data patterns are synchronous bits at this phase point. In this example, it is assumed that the synchronization bit is composed of 32 bits.

That is, in the pattern detection unit 1, all eight columns of data patterns out of eight data patterns have synchronization bits (for example, "
11110110'') is detected.

The data pattern is, for example, the first column repeats A data bit, A' data bit, A data bit sequentially, and the second column repeats B data bit 1-, B' data bit, and so on. It is assumed that the B data bit is repeated, and the 8th column is the H data bit l-, H' data bit, and H data bit are repeated.

Next, in the pattern detection section 1, for example, as shown in FIG.
(1)) 8 repetitions at phase points If the data patterns at the phase points all match in synchronization bits, the matching pulses at the 8 data patterns are extracted by gates 01 to G8, and the data pattern Establishment of synchronization is attempted by corresponding synchronization protection circuits #1 to #8.

Then, the results of the protection processing of the synchronization protection circuits #l to #8 are sent out as a control signal to the channel switching section 5 that switches channels of data at each phase point.

The timing for taking synchronization protection in each synchronization protection circuit #1 to synchronization protection circuit #8 is determined by counting the timing when a coincidence pulse is taken from the gates G1 to G8 and the clock CLK from a clock generator (not shown), for example. It is assumed that the timing when the count value is output from the frame counter 42 matches.

Further, when outputting the results of the synchronization protection in each of the synchronization protection circuits #1 to #8, the clock CLK is temporarily blocked from passing through the AND circuit 44 via the gate circuit 31.

Furthermore, as a result of synchronization protection in each synchronization protection circuit #1 to synchronization protection circuit #8, when synchronization is achieved as shown in the data pattern of the phase point (b) in Figure 5 (B) (1), a zero signal is generated. At this time, the channel switching unit 5 outputs the eight columns of parallel data without switching them.

On the other hand, when the data pattern is in an asynchronous state such as the data pattern having phase points (b)' and (b)'' as shown in FIG. N= from the F.F circuit n+1 of the last column of the pattern detection section 1 is used as a control signal to replace the parallel data of 8 columns.
The output of 8 columns and (N
-1) = 7 column output.

For example, if the data is separated into 8 columns at the phase points }(b)' and (b)'' as shown in Figure 5 (B') (2) and (3), each column is assumed to be out of synchronization. After synchronization is established in synchronization protection circuit #1 to synchronization protection circuit #8, the channel switching unit 5 converts 8 columns using the 8 columns of data in F, F circuit n+1 and the 7 columns of data in F, F circuit n+1. The data in Figure 5 (B) (2), (3)
The data pattern is replaced as shown in the data pattern output shown in FIG. 5(C).

That is, in the case of Figure 5 (B) (2), the A data bit in the 8th column is placed in the 1st column, the 2nd column is replaced with the B data bit, and the 3rd column is replaced with the C data bit. , in the case of Fig. 5 (3), the A data bit in the 7th column is placed in the 1st column, the B data bit in the 8th column is placed in the 2nd column, and the C data bit in the 1st column of the next phase is placed in the 1st column. Swap the data bits so that they are in the third column.

These replacements are performed for each synchronization protection circuit #1 as described above.
After synchronization is established in synchronization protection circuit #8, backward protection is performed and the output signal is used as a control signal.

[Problem to be solved by the invention]

In the conventional circuit configuration as explained in FIG. 3, that is, when serial data is converted into N columns of parallel data, N types of data patterns are detected and synchronization is detected for each. Since a synchronization protection circuit is required for each pattern, the larger the number of parallel data, the larger the circuit scale, which may make it difficult to implement in a miniaturized device.

Also, if an asynchronous state is detected, try to establish synchronization so that it becomes a synchronous state, and after taking that protection (after backward protection)
Since the data is replaced with the normal data pattern state, there is a problem that the processing becomes longer by the number of backward protection stages.

An object of the present invention is to provide a synchronization detection circuit that can efficiently establish synchronization of a plurality of parallel data with a simple circuit configuration.

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the synchronization detection circuit of the present invention.

The principle diagram of the synchronization detection circuit of the present invention shown in FIG.
and a condition setting means 60. The latch means 20 described above has N types of data that are output when all the data of the N types of data patterns detected by the pattern detection section 1 match with the synchronization bits. The protection means 30 sequentially selects the N types of coincidence pulses detected by the pattern detection section 1 by the output of the latching means 20, and
The condition setting means 60 protects the synchronization of N parallel data based on each matching pulse.
This is to set the conditions for sending out a signal that controls the switching of N parallel data in the channel switching unit 5 based on the timing when 0 takes synchronization protection, and by providing such means, this problem is solved. as a means to do so.

[Function] The matching pulse output based on the data pattern detected by the pattern detection section 1 is latched in the latch means 20, and the synchronization of parallel data is performed based on the matching pulses sequentially selected by one protection means 30 using the latch output. Take protection.

Then, a control signal for exchanging N parallel data patterns at the timing of the first stage of backward protection in one protection means 30 is output to the channel exchanging unit 5.

The output conditions of the control signal for switching the N parallel data patterns in the channel switching unit 5 in the first stage of backward protection in the protection unit 30 are set and outputted by the condition setting unit 60.

In this way, by configuring one protection means 30 for N types of data patterns of N parallel data, and replacing the N parallel data at the time of first establishing synchronization,
The circuit size does not increase in proportion to the number of parallel data.
Moreover, it becomes possible to efficiently exchange data in parallel.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a diagram illustrating an embodiment of the synchronization detection circuit of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The synchronization detection circuit 300 in FIG. 2 separates serial data into eight columns of parallel data in the same way as explained in FIG. , a synchronization protection section 30a as the protection means 30, and a condition setting section 6 as the condition setting section 40.
This is an example configured from 0a.

Note that the present embodiment shown in FIG.
In addition to 0a and 60a, the pattern detection section 1, timing generation section 4, and CH switching section 5, which perform the same operations as those described in FIG. 3, are provided.

The above-mentioned latch unit 20a detects and outputs eight data patterns by the pattern detection unit 1 (an example when n=8).
The 8 types of coincidence pulses that are output when all 8 columns of data match with the synchronization bits are sent to 8 gate circuits.
Eight F.1 to G8 latches outputs respectively. It is composed of F.F circuits, and FIG. 2 shows a representative F.F. This shows the F circuit.

The synchronization protection unit 30a also includes a selector (SEL) 31 that sequentially selects one of the coincidence pulses taken out from each gate circuit 01 to G8, and synchronization protection of parallel data using the coincidence pulse selected by the selector (SEL) 31. The condition setting unit 60a performs an AND operation to set the conditions for making the result output of the synchronization protection circuit 32 the first stage of backward protection.
This is an example constructed from @ roads.

It is assumed that the timing generator 4 in the embodiment shown in FIG. 2 also uses the clock CLK from a clock generator (not shown) as a timing signal.

The latch unit 20a latches eight types of coincidence pulses outputted from the pattern detection unit 1 through the gates G1 to G8, and uses this latch output to cause the synchronization protection unit 30 to
The internal selector (SEL) 3■ selects the outputs of the gates 1-Gl, one by one, sequentially from the outputs of the gates 1-G1, for example.

Then, based on the coincidence pulse selected by the selector (SEL) 31, the synchronization protection circuit 32 protects the parallel data from synchronization.

The timing for taking this synchronization protection is determined by the signal when the mismatch detection circuit 43 in the timing detection section 4 detects that the output of the pattern detection section 1 and the output when the clock CLK is counted by the frame counter 42 match. by.

Further, the output when counted by the frame counter 42 is taken in as one of the three inputs of the AND circuit forming the condition setting section 60a, and the other one of the three inputs of the AND circuit is the output of the synchronization protection circuit 32. and the other is gate G1
It consists of the inverted output of the OR circuit 41 which is the logical sum of the outputs of G8 to G8, thereby creating the conditions for outputting the following control signal at the first stage of backward protection in the synchronization protection circuit 32.

That is, the data latched in the latch section 20a is taken out and used as a selection control signal for the selector (SEL) 31, and also as a CH switching control signal for the CH switching section 5.

Note that the data pattern to be replaced in the CH replacement section 5 is the output of the same pattern detection section 1 as explained in FIG.

In the embodiment shown in FIG. 2, even if the number of parallel data to be separated increases, the number selected by the selector (SEL) 31 is correspondingly increased, and the F. It can be constructed by simply increasing the number of F circuits.

Also, the timing of switching in the CH switching section 5 is as follows:
By performing replacement at the first stage of backward protection in the synchronization protection circuit 32, replacement processing can be performed early, and overall processing time can be shortened and efficiency can be improved.

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide a synchronization detection circuit that has a simple configuration and can establish efficient synchronization.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the principle of the synchronization detection circuit of the present invention, Figure 2 is a diagram explaining an embodiment of the synchronization detection circuit of the invention, and Figure 3 is a diagram explaining a conventional example of the Tsubaki synchronization detection circuit. , FIG. 4 is a diagram illustrating an example of the use of the synchronization detection circuit, and FIG. 5 is a diagram illustrating an example of separating serial data into parallel data. In the figure, l is a pattern detection section, 3.30a is a synchronization protection section,
4 is a timing generation section, 5 is a CH switching section, 20 is a latch means, 20a is a latch section, 30 is a protection means, 31 is a selector (SEL), 32 is a synchronization protection circuit, 33
41 is a gate circuit, 41 is an OR circuit, 42 is a frame counter, 43 is a mismatch detection circuit, and 60 is a condition setting means. 44 is an AND circuit, and 60a is a condition setting section. Figure 5 explains the minute X9J to

Claims (1)

[Claims] Serial data to serial/parallel converter (200)
When converting to N-parallel data, N-parallel detects N frame patterns of the parallel data based on the order in which the data bits are arranged in parallel, and all of the data in the N-parallel data patterns are synchronized. a pattern detection unit (1) that outputs N types of matching pulses that are output when bits match; and a timing creation unit (1) that creates timing for taking synchronization protection for N parallel data based on the N types of matching pulses.
4); and a channel switching unit (5) for replacing N parallel data outputted from the pattern detection unit (1) to a synchronous pattern, the synchronization detection circuit (300) comprising: a latch means (20) for sequentially latching the N types of coincidence pulses detected and output by the detection section (1); a protection means (30) that protects the synchronization of N parallel data based on the coincidence pulses of the channel switching unit (5); ) is provided with a condition setting means (60) for setting a condition for setting the time when the first stage of rearward protection is processed.