JPH022309B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MOS integrated circuit (hereinafter referred to as CMOS).
This relates to electrostatic protection devices (referred to as ICs).

CMOS ICs are generally susceptible to damage caused by static electricity, and as patterns become finer in recent years, the thickness of the gate oxide film has also become thinner, so the role of electrostatic protection devices has become increasingly important. There is.

An object of the present invention is to provide a semiconductor device equipped with a protection device that is resistant to damage caused by static electricity.

According to the present invention, a semiconductor substrate of one conductivity type, a region of another conductivity type formed in the semiconductor substrate of one conductivity type, and an insulated gate field effect transistor formed in the semiconductor substrate and the region of another conductivity type, respectively. a second diode connected to the gate of an insulated gate field effect transistor formed in the other conductivity type region with the other conductivity type region as one electrode; and means for applying a potential to the other conductivity type region; A semiconductor device is obtained that includes a resistor formed of a region of another conductivity type connected between a second diode and means for applying a potential to the region of another conductivity type.

Next, the drawings will be explained.

FIG. 1 is a plan view of a conventional electrostatic protection device, and FIG. 2 is a cross-sectional view of FIG. 1 taken along the dotted line. A P channel type MOS field effect transistor is formed in an N type semiconductor substrate 9, and a P well region 1 with a relatively low impurity concentration is formed on the N type semiconductor substrate 9.
An N-channel type MOS field effect transistor is formed in . These P channel type and N
The gates of the channel type MOS field effect transistors are both connected to an input terminal and to an electrostatic protection device. Figures 1 and ^{2 show} this electrostatic ^protection device ^. The resistance between the wiring 4 that provides _SS and the connection part 7 is as follows: the resistance R 1 connected to one side 100 of the N ⁺ -P ⁺ diode is the smallest, and the resistance R ₁ connected to one side 100 of the N + -P + diode is the smallest, and the resistance is connected to the one side 100 in the order of resistance value. Objects (those connected to one side 200, things connected to one side 300) <things connected to one side 400.
These resistors are mainly formed in the P ⁺ region 3. For this reason, on one side 100 of the N ⁺ region 2,
Since the current tends to concentrate and only one of the four sides of the effective diode is utilized, the P ⁺ -N ⁺ junction on this one side 100 is likely to be destroyed. Board 1
A P ⁺ −N ⁺ diode for electrostatic damage protection is also formed in the P + -N + diode, which is in contact with the wiring that supplies the power supply potential to the substrate 1, compared to the diode formed in the N ⁺ region 2 and P ⁺ region 3. Since the portion is sufficiently far away from the diode, all four sides are effectively utilized on average, resulting in high breaking strength.

FIG. 3 is a plan view showing one embodiment of the present invention, and FIG. 4 is a sectional view taken along the dotted line. Similar to the conventional example, P channel type and N channel type are formed in the N type substrate 19 and the P well 11, respectively.
A MOS field effect transistor is formed,
These gates are both connected to an input terminal and a diode for electrostatic damage protection. Electrostatic breakdown protection diodes are formed in the substrate 19 and the P-well 11, respectively, and FIGS. 3 and 4 show diodes formed in the P-well 11. An N ⁺ region 12 and a P ⁺ region 13 are formed in the P well 11, and these constitute a diode.
A portion where the P+ region 13 is not provided is provided on the surface of the P-well 11 between the connection portion with the wiring 14 that applies the power supply voltage V _SS to the P ^- well 11 and the N ⁺ region 12.
This constitutes a resistor _R1 having a resistance value ten times or more (several kΩ or more) than that of the conventional example. Therefore, the effective surface of the diode composed of the N ⁺ region 12 and the P ⁺ region 13 is approximately all four, and current does not concentrate on one side. Therefore, it is possible to obtain a breakdown strength almost equivalent to that of a diode for electrostatic breakdown protection provided on the substrate 19 (not shown).

Note that the wiring 16 connects the N ⁺ region 12 to the common gate connection portion and input terminal of the MOS field effect transistors formed in the substrate 19 and the P well 11, respectively, via the connection portion 16.

In this example, a case in which a P-well is formed on an N-type substrate has been described, but it goes without saying that similar measures can be taken by changing the polarity for a case in which an N-well is formed on a P-type substrate.

[Brief explanation of drawings]

FIG. 1 is a plan view of a typical conventional protection device, and FIG. 2 is a sectional view taken along the dotted line in FIG. FIG. 3 is a plan view showing an embodiment of the present invention, and FIG. 4 is a sectional view taken along the dotted line in FIG. 1, 11...P well, 2, 12...N ⁺ area,
3,13...P ⁺ area, 4,14...Wiring, 5,
15... Wiring, 6, 16... Connection part, 7, 17...
...Connection part, 9, 19...N type board.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a well region of the opposite conductivity type formed in the semiconductor substrate, a high concentration region of one conductivity type formed approximately at the center of the well region, and a high concentration region of the one conductivity type formed approximately in the center of the well region. A high concentration region of opposite conductivity type forming a diode in contact with almost all sides of the high concentration region, and a resistance region of opposite conductivity type extending in a band shape from a part of the side surface of the well region. 1. A semiconductor device comprising: an end of the resistance region connected to a voltage terminal; and a region of one conductivity type connected to an external terminal.