JPH022334B2 - - Google Patents
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- Publication number
- JPH022334B2 JPH022334B2 JP2653981A JP2653981A JPH022334B2 JP H022334 B2 JPH022334 B2 JP H022334B2 JP 2653981 A JP2653981 A JP 2653981A JP 2653981 A JP2653981 A JP 2653981A JP H022334 B2 JPH022334 B2 JP H022334B2
- Authority
- JP
- Japan
- Prior art keywords
- waveform
- circuit
- level
- intersymbol interference
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
Landscapes
- Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】
本発明はPCM伝送システムにおける伝送路よ
り歪を受けたパルス波形を等化する回路を制御す
るための符号間干渉検出回路に係り簡単な回路で
実現出来る符号間干渉検出回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an intersymbol interference detection circuit for controlling a circuit that equalizes a pulse waveform distorted by a transmission line in a PCM transmission system, and intersymbol interference detection that can be realized with a simple circuit. Regarding circuits.
第１図に符号間干渉検出回路を用いた等化回路
のブロツク構成図を示す。図中２１は等化器、２
２は符号間干渉検出回路、２３は識別回路であ
る。この回路としては等化器２１により伝送線路
の損失特性の補正、及び波形整形を行ない識別回
路２３にて多値レベルを識別してその結果を出力
している。符号間干渉検出回路２２は識別回路２
３より多値レベルの識別結果と等化器２１より等
化波形を供給され符号間干渉を検出しこの出力を
等化回路２１に供給して符号間干渉を小さくして
いる。第２図に従来の符号間干渉検出回路の例と
して６値伝送の場合の回路を示す。第３図に第２
図の場合のアイパタンを示す。図中１〜１１はフ
リツプフロツプ回路（以下FFと称す）、１２〜１
６はAND回路、１７はOR回路、１８はｎタイム
スロツトの遅延回路、１９は排他的OR回路、２
０は低域波器、C1〜C11はコンデンサ、R1〜
R22は抵抗、V1，V2は直流電圧、レベル１〜１１
の中奇数は多値レベル、偶数は等化波形の振巾を
識別する識別レベルを示す。又レベル１〜１１は
FF１〜１１に対応しておりFF１〜１１の入力側
に直流電圧V1，V2の差を抵抗で分割して各多値
レベルに対応させている。例えばFF１の場合は
抵抗R1，R2で分割してレベル１に対応させてい
る。又レベル６は０レベルでレベル１の方向が正
レベル１１の方向が負である。FF１〜１１内の
Ｑ及びは相補出力を示す。FF２のの出力と
FF３のＱの出力をAND回路１２によりANDを
とつた出力はレベル２と３の間に等化波形があれ
ば“１”を出力する。FF４とFF５，FF６とFF
７，FF８とFF９，FF１０とFF１１の組合せの
場合も上記と同様である。FF１のＱの出力はレ
ベル１以上に等化波形があれば“１”を出力す
る。AND回路１２〜１６の出力及びFF１のＱの
出力をOR回路１７にてORをとり上記のどれか
の出力が“１”ならば１を出力している。即ち多
値の等化波形が正の場合では多値レベルをこす場
合“１”を出力し、負の場合では等化波形が多値
レベルをこさない場合“１”を出力している。こ
の出力が等化波形の符号間干渉の極性を表わして
いる。又FF６のＱの出力は等化波形が正ならば
“１”負であれば“０”を出力する。これを遅延
回路１８にてｎタイムスロツト遅延させ排他的
OR回路１９に入力している。OR１７の出力と
遅延回路１８の出力を排他的OR回路１９に出力
し符号間干渉の極性とｎタイムスロツト前の等化
波形の極性が合致している時は“０”を出力し合
致していない時は“１”を出力している。この出
力を低域波器２０を介することにより平均をと
り符号間干渉としている。この回路では多値レベ
ルのどこに等化波形の振巾があつてもｎタイムス
ロツト前の等化波形の極性と符号間干渉の極性が
合致しているかどうか判定しこれによるパルス出
力を平均化して符号間干渉を検出しているので回
路が複雑になる欠点があつた。 FIG. 1 shows a block diagram of an equalization circuit using an intersymbol interference detection circuit. In the figure, 21 is an equalizer, 2
2 is an intersymbol interference detection circuit, and 23 is an identification circuit. In this circuit, an equalizer 21 corrects the loss characteristics of the transmission line and shapes the waveform, and a discriminator circuit 23 discriminates multilevel levels and outputs the results. The intersymbol interference detection circuit 22 is the identification circuit 2
The multilevel discrimination result from 3 and the equalized waveform from the equalizer 21 are supplied, intersymbol interference is detected, and this output is supplied to the equalization circuit 21 to reduce the intersymbol interference. FIG. 2 shows a circuit for six-value transmission as an example of a conventional intersymbol interference detection circuit. Figure 3 shows the second
The eye pattern in the case shown in the figure is shown. In the figure, 1 to 11 are flip-flop circuits (hereinafter referred to as FF), 12 to 1
6 is an AND circuit, 17 is an OR circuit, 18 is a delay circuit with n time slots, 19 is an exclusive OR circuit, 2
0 is a low frequency amplifier, C 1 to C 11 are capacitors, R 1 to
R 22 is a resistance, V 1 and V 2 are DC voltages, levels 1 to 11
Among them, odd numbers indicate multilevel levels, and even numbers indicate discrimination levels for identifying the amplitude of the equalized waveform. Also, levels 1 to 11 are
It corresponds to FFs 1 to 11, and the difference between DC voltages V 1 and V 2 is divided by a resistor on the input side of FFs 1 to 11 to correspond to each multi-value level. For example, in the case of FF1, it is divided by resistors R 1 and R 2 to correspond to level 1. Further, level 6 is the 0 level, and the direction of level 1 is positive and the direction of level 11 is negative. Q and in FF1 to FF11 indicate complementary outputs. FF2's output and
The output obtained by ANDing the Q output of FF3 by the AND circuit 12 outputs "1" if there is an equalized waveform between levels 2 and 3. FF4 and FF5, FF6 and FF
7. The same applies to the combinations of FF8 and FF9, and FF10 and FF11. The Q output of FF1 outputs "1" if there is an equalized waveform at level 1 or higher. The outputs of the AND circuits 12 to 16 and the Q output of FF1 are ORed in an OR circuit 17, and if any of the above outputs is "1", 1 is output. That is, when the multi-value equalized waveform is positive, it outputs "1" when it crosses the multi-value level, and when it is negative, when the equalized waveform does not cross the multi-value level, it outputs "1". This output represents the polarity of the intersymbol interference of the equalized waveform. Further, the output of Q of FF6 is "1" if the equalized waveform is positive, and "0" if it is negative. This is delayed by n time slots in the delay circuit 18 and exclusive
It is input to the OR circuit 19. The output of the OR 17 and the output of the delay circuit 18 are output to the exclusive OR circuit 19, and when the polarity of the intersymbol interference matches the polarity of the equalized waveform n time slots ago, it outputs "0". When there is none, "1" is output. This output is passed through a low frequency filter 20 to be averaged and used as intersymbol interference. This circuit determines whether the polarity of the equalized waveform n time slots ago matches the polarity of the intersymbol interference, no matter where the amplitude of the equalized waveform is at the multilevel level, and averages the resulting pulse output. Since it detects intersymbol interference, it has the disadvantage that the circuit becomes complicated.
回路の伝達特性は、正パルス、負パルスに対し
同等の応答を示す。従つて正パルスに対し符号間
干渉があれば同一の符号間干渉が負パルスに対し
ても生ずる。よつて符号間干渉量の検出には正又
は負のどちらか一方に限定しても問題はない。又
通常符号間干渉量を検出してから等化回路の制限
を行う迄の応答時間は、パルス繰り返し速度に比
較して非常に遅い為、干渉量の抽出確率が多少劣
化しても実用上差支えない。 The transfer characteristics of the circuit show equivalent responses to positive and negative pulses. Therefore, if there is intersymbol interference for positive pulses, the same intersymbol interference will also occur for negative pulses. Therefore, there is no problem in detecting the amount of intersymbol interference even if it is limited to either positive or negative. In addition, the response time from detecting the amount of intersymbol interference to limiting the equalization circuit is usually very slow compared to the pulse repetition rate, so there is no practical problem even if the probability of extracting the amount of interference deteriorates to some extent. do not have.
これ等の点に着目し、本発明は、回路を簡易化
出来る符号間干渉検出回路の提供を目的としてい
る。 Focusing on these points, the present invention aims to provide an intersymbol interference detection circuit whose circuit can be simplified.
本発明は上記の目的を達成するためにPCM伝
送システムにおける伝送路より歪を受けた多値パ
ルス波形を等化する回路を制御するための符号間
干渉検出回路において、クロツクのタイミング
で、等化波形の極性が正か負かを求め、又極性を
求めた時刻よりｎタイムスロツト後のクロツクの
タイミングで、該等化波形が予め定めた多値レベ
ルのパルスの時、該等化波形が、該多値レベルよ
り上記求めた極性と同方向にあるか異方向にある
かで該等化波形の符号間干渉の極性の情報を求
め、該等化波形が予め定めた多値レベルのパルス
でない時は、以前に求めた情報を継続し、これ等
の情報を平均化して、上記等化する回路を制御す
る出力を得るようにしたことを特徴とする符号間
干渉検出回路の提供である。 To achieve the above object, the present invention provides an intersymbol interference detection circuit for controlling a circuit that equalizes a multivalued pulse waveform distorted by a transmission line in a PCM transmission system. Find out whether the polarity of the waveform is positive or negative, and when the equalized waveform is a predetermined multi-level pulse at a clock timing n time slots after the time when the polarity was found, the equalized waveform becomes Information on the polarity of the intersymbol interference of the equalized waveform is obtained from the multilevel level based on whether it is in the same direction as the polarity obtained above or in a different direction, and the equalized waveform is not a pulse of a predetermined multilevel level. Another object of the present invention is to provide an intersymbol interference detection circuit characterized in that the previously obtained information is continued and the information is averaged to obtain an output for controlling the equalization circuit.
以下本発明の実施例につき図に従つて説明する
第４図は本発明の実施例の６値伝送の場合のブロ
ツク構成図、第８図は第４図に対応する１例の等
化波形図で、第８図の等化波形はクロツクのタイ
ミングのイ点にてレベル６より正方向にあるの
で、極性は正であり、符号間干渉を求める２タイ
ムスロツト後のクロツクのタイミングのロ点で
は、レベル８と１０の間にある多値レベル９に該
当するもので、多値レベル９より上記極性と同方
向の正方向にある場合を示している。 Embodiments of the present invention will be explained below with reference to the drawings. FIG. 4 is a block configuration diagram in the case of six-value transmission according to the embodiment of the present invention, and FIG. 8 is an equalized waveform diagram of an example corresponding to FIG. 4. Therefore, since the equalized waveform in Figure 8 is in the positive direction from level 6 at the clock timing point A, the polarity is positive, and at the clock timing point C after two time slots where intersymbol interference is sought. , corresponds to multivalue level 9 between levels 8 and 10, and indicates a case in which the polarity is more positive than multivalue level 9 in the same direction as the above polarity.
等化波形の極性と同方向であることは、等化波
形を弧立等化波形と考えた場合、点線のハに示す
如く符号間干渉の方向は正であることを意味し、
（この場合は第４図では、極性と同方向であるの
でFF２８よりは“１”を出力する）等化波形を
負方向に制御すればよいことになる。 Being in the same direction as the polarity of the equalized waveform means that when the equalized waveform is considered as a vertical equalized waveform, the direction of intersymbol interference is positive as shown by the dotted line C.
(In this case, in FIG. 4, since it is in the same direction as the polarity, "1" is output from the FF 28.) It is sufficient to control the equalization waveform in the negative direction.
又負方向であることは、孤立等化波形と考えた
場合、符号間干渉の方向は負であることを意味
し、（第４図ではFF２８よりは“０”を出力す
る）等化波形を正方向に制御すればよいことにな
る。で、符号間干渉抽出条件を識別レベル８と１
０の間のレベル（誤差）及びｎタイムスロツト前
のパルスの極性が正パルスであるという場合に限
定し回路を簡単にしたものである。第５図は第４
図の各点のパルス波形のタイムチヤートを示す。
図中第２図と同一機能のものは同一記号で表示し
てある。又レベル関係は第３図を参照のこと。２
６はｎタイムスロツトの遅延回路、２７はAND
回路、２８はFF回路、２９は低域波器、ａ，
ｂ，ｃ，ｄ，ｅ，ｆ，ｇ，ｈはこの記号を付した
点のパルス波形を示す為の記号で第５図のａ，
ｂ，ｃ，ｄ，ｅ，ｆ，ｇ，ｈにこれに対応したパ
ルス波形を示している。ａはFF６のＱの出力パ
ルス波形で等化波形の極性が正の時“１”で、負
の時“０”となる、ｂはａのパルスを遅延回路２
６にてｎ＝２とした場合即ち２タイムスロツト遅
延させたパルス波形、ｃはレベル８より負の方向
に等化波形がきた時“１”を出力することを示す
パルス波形、ｄはレベル１０より正の方向に等化
波形がきた時“１”を出力することを示すパルス
波形、ｅはクロツク波形でFFはパルスの立上り
で動作するので立上りをつくるためにRZ波形に
直す役目をしている。ｆはAND回路２７の出力
パルス波形、ｇはレベル９よりレベル８側に等化
波形がある場合“１”を出力することを示すパル
ス波形、ｈはFF２８の出力パルス波形である。
或る孤立等化波形のｎタイムスロツト後の符号間
干渉を見るには符号間干渉を見るクロツクのタイ
ミングの等化波形がレベル８と１０の間にあり
〔ｃ，ｄが共に“１”のパルス波形の場合〕尚か
つそれよりｎタイムスロツト前の時刻の等化波形
の極性が正の場合〔ａが“１”のパルス波形で第
５図ではｎ＝２の場合を示しているので２タイム
スロツト後はｂが“１”のパルス波形となる。〕
即ち第５図ではｂ，ｃ，ｄが共に“１”のパルス
波形でｆに示すAND回路２７の出力パルス波形
が“１”で符号間干渉を見る等化波形がレベル９
より正の方向ならばFF９の出力は“１”となり
FF２８の出力を“１”とし、“０”ならば“０”
としこの状態を次のAND回路２７の出力が“１”
の時迄持続し、これにより得られる出力を低域
波器２９にて平均することにて符号間干渉が求め
られる。尚第２図に示すFFの入力側直流多値レ
ベル設定回路を含み、FF８，９，１０はそれぞ
れFF２，３，４又はFF４，５，６又はFF６，
７，８でもよいわけである。 Also, the negative direction means that the direction of intersymbol interference is negative when considered as an isolated equalized waveform (in Figure 4, FF28 outputs "0"). It is only necessary to control it in the positive direction. Then, the intersymbol interference extraction conditions are set to discrimination levels 8 and 1.
The circuit is simplified and limited to cases where the level (error) is between 0 and the polarity of the pulse before n time slots is a positive pulse. Figure 5 is the 4th
A time chart of the pulse waveform at each point in the figure is shown.
Components in the figure that have the same functions as those in FIG. 2 are indicated by the same symbols. Also, please refer to Figure 3 for the level relationship. 2
6 is a delay circuit of n time slots, 27 is an AND
circuit, 28 is an FF circuit, 29 is a low frequency device, a,
b, c, d, e, f, g, h are symbols to indicate the pulse waveforms at the points with these symbols, and are a,
The corresponding pulse waveforms are shown in b, c, d, e, f, g, and h. a is the output pulse waveform of Q of FF6, and when the polarity of the equalized waveform is positive, it is "1" and when it is negative, it is "0".
When n=2 in 6, that is, the pulse waveform delayed by 2 time slots, c is the pulse waveform indicating that "1" is output when the equalized waveform comes in the negative direction from level 8, and d is the pulse waveform at level 10. A pulse waveform that indicates that "1" is output when the equalization waveform comes in a more positive direction. e is a clock waveform and FF operates on the rising edge of the pulse, so it plays the role of converting it to an RZ waveform to create a rising edge. There is. f is an output pulse waveform of the AND circuit 27, g is a pulse waveform indicating that "1" is output when there is an equalized waveform on the level 8 side from level 9, and h is an output pulse waveform of the FF 28.
To check the intersymbol interference after n time slots of a certain isolated equalized waveform, the equalized waveform whose clock timing is between levels 8 and 10 [where both c and d are "1"] In the case of a pulse waveform] And if the polarity of the equalized waveform at a time n time slots before is positive [a is a pulse waveform of "1" and Fig. 5 shows the case where n = 2, so 2 After the time slot, b becomes a pulse waveform of "1". ]
That is, in FIG. 5, b, c, and d are all "1" pulse waveforms, the output pulse waveform of the AND circuit 27 shown in f is "1", and the equalized waveform for observing intersymbol interference is level 9.
If the direction is more positive, the output of FF9 will be “1”.
The output of FF28 is “1”, and if it is “0”, it is “0”
Then, the output of the next AND circuit 27 is “1” in this state.
The inter-symbol interference is determined by averaging the output obtained by this in the low-band filter 29. In addition, it includes the DC multi-level setting circuit on the input side of the FF shown in FIG.
7 or 8 would be fine.
本発明の他の実施例を第６図第７図に示す。図
中第２図第４図と同一機能のものは同一記号で表
す。３０はAND回路である。本実施例の第４図
と異なる点は第４図ではレベル８，１０の間に符
号間干渉を求める等化波形がある場合該等化波形
がレベル９上を越えるか越えないかを見ていたが
第６図第７図は符号間干渉を求める等化波形を多
値レベルの両端にて監視する場合で２つのレベル
間でなく１つのレベル以上にある場合、第６図で
はレベル２よりレベル１の方向第７図ではレベル
１０よりレベル１１の方向に等化波形がある場合
レベル１上及びレベル１１上を該等化波形が越え
るか越えないかで符号間干渉を見ている点であ
る。従つて回路はさらに簡単になつている。 Other embodiments of the invention are shown in FIGS. 6 and 7. Components with the same functions as those in FIGS. 2, 4, and 4 are indicated by the same symbols. 30 is an AND circuit. The difference from FIG. 4 of this embodiment is that in FIG. 4, when there is an equalized waveform for which intersymbol interference is sought between levels 8 and 10, it is checked whether the equalized waveform exceeds level 9 or above. However, when the equalized waveform for determining intersymbol interference is monitored at both ends of the multilevel level, and when the equalized waveform for finding intersymbol interference is monitored at one level or more, instead of between two levels, the Direction of Level 1 In Figure 7, if there is an equalized waveform in the direction from level 10 to level 11, intersymbol interference is considered based on whether or not the equalized waveform exceeds levels 1 and 11. be. The circuit therefore becomes even simpler.
以上詳細に説明した如く本発明によれば回路が
簡単で安価になる効果がある。 As described above in detail, the present invention has the effect of making the circuit simple and inexpensive.
第１図は符号間干渉検出回路を用いた等化回路
のブロツク構成図、第２図は従来の符号間干渉検
出回路の例として６値伝送の場合の回路、第３図
は第２図の場合のアイパタン、第４図は本発明の
実施例の６値伝送の場合のブロツク構成図、第５
図は第４図の各点のパルス波形のタイムチヤート
でａはFF６のＱの出力パルス波形、ｂはａのパ
ルスを遅延回路２６にてｎ＝２とした場合即ち２
タイムスロツト遅延したパルス波形、ｃはレベル
８より負の方向に等化波形がきた時“１”を出力
することを示すパルス波形、ｄはレベル１０より
正の方向に等化波形がきた時“１”を出力するこ
とを示すパルス波形、ｅはクロツク波形、ｆは
AND回路２７の出力パルス波形、ｇはレベル９
よりレベル８側に等化波形がある場合“１”を出
力することを示すパルス波形、ｈはFF２８の出
力パルス波形、第６図、第７図は本発明の別の実
施例、第８図は第４図に対応する１例の等化波形
図である。図中１〜１１，２８はFF、１２〜１
６，２７，３０はAND回路、１７はOR回路、１
８，２６はｎタイムスロツトの遅延回路、１９は
排他的OR回路、２０，２９は低域波器、C1〜
C11はコンデンサ、R1〜R22は抵抗、V1，V2は直
流電圧、レベル１〜１１の中奇数は多値レベル、
偶数は多値レベルを識別する識別レベル、２１は
等化器、２２は符号間干渉検出回路、２３は識別
回路、である。
Figure 1 is a block diagram of an equalization circuit using an intersymbol interference detection circuit, Figure 2 is an example of a conventional intersymbol interference detection circuit for six-value transmission, and Figure 3 is the same as that shown in Figure 2. Fig. 4 is a block configuration diagram in the case of six-value transmission according to the embodiment of the present invention;
The figure is a time chart of the pulse waveform at each point in FIG.
The pulse waveform delayed by the time slot, c is the pulse waveform that indicates that "1" is output when the equalization waveform comes in the negative direction from level 8, and d shows that "1" is output when the equalization waveform comes in the positive direction from level 10. The pulse waveform indicates that 1" is output, e is the clock waveform, and f is the clock waveform.
Output pulse waveform of AND circuit 27, g is level 9
A pulse waveform indicating that "1" is output when the equalized waveform is closer to level 8, h is the output pulse waveform of FF28, FIGS. 6 and 7 are another embodiment of the present invention, and FIG. 8 is an example of an equalized waveform diagram corresponding to FIG. 4; In the figure, 1 to 11, 28 are FF, 12 to 1
6, 27, 30 are AND circuits, 17 is OR circuit, 1
8 and 26 are n time slot delay circuits, 19 is an exclusive OR circuit, 20 and 29 are low frequency generators, and C 1 to
C 11 is a capacitor, R 1 to R 22 are resistors, V 1 and V 2 are DC voltages, odd numbers among levels 1 to 11 are multi-value levels,
Even numbers are identification levels for identifying multilevel levels, 21 is an equalizer, 22 is an intersymbol interference detection circuit, and 23 is an identification circuit.
Claims (1)
受けた多値パルス波形を等化する回路を制御する
ための符号間干渉検出回路において、クロツクの
タイミングで、等化波形の極性が正か負かを求
め、又極性を求めた時刻よりｎタイムスロツト後
のクロツクのタイミングで、該等化波形が予め定
めた多値レベルのパルスの時、該等化波形が、該
多値レベルより上記求めた極性と同方向にあるか
異方向にあるかで該等化波形の符号間干渉の極性
の情報を求め、該等化波形が予め定めた多値レベ
ルのパルスでない時は、以前に求めた情報を継続
し、これ等の情報を平均化して、上記等化する回
路を制御する出力を得るようにしたことを特徴と
する符号間干渉検出回路。1. In the intersymbol interference detection circuit that controls the circuit that equalizes the multi-level pulse waveform distorted by the transmission line in the PCM transmission system, the polarity of the equalized waveform is determined at clock timing to determine whether it is positive or negative. , and when the equalized waveform is a pulse of a predetermined multilevel level at a clock timing n time slots after the time when the polarity was determined, the equalized waveform has the polarity determined above based on the multilevel level. Obtain information on the polarity of intersymbol interference of the equalized waveform depending on whether it is in the same direction or in a different direction, and if the equalized waveform is not a predetermined multi-level pulse, continue the previously obtained information. An intersymbol interference detection circuit characterized in that the information is averaged to obtain an output for controlling the equalization circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2653981A JPS57141143A (en) | 1981-02-25 | 1981-02-25 | Intercode interference detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2653981A JPS57141143A (en) | 1981-02-25 | 1981-02-25 | Intercode interference detecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57141143A JPS57141143A (en) | 1982-09-01 |
| JPH022334B2 true JPH022334B2 (en) | 1990-01-17 |
Family
ID=12196294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2653981A Granted JPS57141143A (en) | 1981-02-25 | 1981-02-25 | Intercode interference detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57141143A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0520400U (en) * | 1991-08-16 | 1993-03-12 | 株式会社ヒユーブレイン | Equipment for mounting components on printed circuit boards |
-
1981
- 1981-02-25 JP JP2653981A patent/JPS57141143A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57141143A (en) | 1982-09-01 |
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