JPH0223422A - Parallel arithmetic unit - Google Patents

Abstract

PURPOSE:To efficiently execute the selective load of a microprogram by designating all unit arithmetic means as the load destination of the same program in accordance with the external instruction and individually designating the load destination of other program. CONSTITUTION:A microprogram is loaded to unit arithmetic means 11-1, 11-2...11-n designated by a load destination designating means 13 with a program loading means 12. The same microprogram is first loaded to all unit arithmetic means 11-1, 11-2,...11-n and next, other microprogram is loaded to the individually designated unit arithmetic means 11-1, 11-2,...11-n. Thus, after the same microprogram is collectively loaded at all unit arithmetic means, another microprogram is individually loaded and written for a part, and therefore, this type of the selective program loading can be performed efficiently.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Effects of the Invention [Summary] The present invention 11i applies to a parallel arithmetic device in which each unit arithmetic circuit simultaneously performs the process, and particularly relates to a parallel arithmetic device in which a microprogram is loaded into each unit arithmetic circuit. The purpose is to provide an arithmetic device, and for this purpose, it has a plurality of unit arithmetic means that simultaneously perform arithmetic operations using a microprogram, a program loading means that loads a microprogram into a specified unit arithmetic means, and a program load means that loads all the units according to external instructions. The present invention is characterized by comprising a load destination specifying means for specifying a calculation means as a load destination of the same program and then individually specifying a load destination of another program.

[Industrial Application Field] The present invention relates to a parallel computing device in which arithmetic processing by a microprogram is performed simultaneously in each unit computing circuit, and particularly relates to a parallel computing device in which a microprogram is loaded into each unit computing circuit. .

JP-A-59-184973, JP-A-60-21818
No. 3, Patent Application No. 1982-258140, Patent Application No. 1983-258
In the apparatus shown in No. 8141, etc., parallel calculations are performed for extracting the outline of a moving object.

In each board used as a unit arithmetic circuit in these devices, microprograms are loaded into RAM, and parallel operations are performed by simultaneously executing the microprograms read out from the RAM.

The microprogram to be loaded into the RAM can be changed arbitrarily, thus increasing the degree of freedom of the device.

Moreover, RAM is a fast memory with low power consumption.
Since it is more suitable than ROM and is easily available, it is advantageous in designing and manufacturing the device.

[Prior Art] FIG. 8 shows a unit 80 that can be used to extract the outline of a moving object in the above-mentioned apparatus, and includes mapping boards 82-1, 82-2, . . . connected to a data bus 81.・82-77
Parallel operations are performed by simultaneously executing operations using .

These calculations are performed by a microprogram, and the microprogram on the host computer 83 is connected to the mapping board 82-1, 82-2 via the data bus 81.
...loaded into 82-77.

Various commands are given from the host computer 83 to the controller board 84 of the unit 80, and the controller board 84 controls the inside of the unit 80 in accordance with the commands.

FIG. 9 shows mapping boards 82-1, 82-2, . The data is written into a microprogram memory 701 composed of a RAM via a gate buffer 714 (three-state buffer).

The microprogram read from the microprogram memory 701 is passed through the pipeline register 702 to the arithmetic circuit 703 (ALU).

(consisting of a memory, etc.), and the arithmetic circuit 703 performs processing according to the microprogram.

Further, the output data of the pipeline register 702 is given to the sequencer 704, and the sequencer 704 uses the input data to control the microprogram memory 7'.
1 read address is obtained.

[Problems to be Solved by the Invention] Here, since the microprogram is loaded into the microprogram memory 701 via the data bus 81,
The bit width of the microprogram is data bus 81
The bit width is limited to less than or equal to the bit width of

Therefore, if the bit width of the data bus 81 is restricted in system construction, the bit width of the microprogram is restricted to less than that, making it difficult to further improve the performance of the system.

Therefore, the device shown in FIG. 10 has been proposed, and the unit 80
A microprogram load line 85 is provided.

A serial data microprogram is sent to the load line 85 from the host computer 83, and the microprogram is sent to the mapping board 82-1.82-2.
...82-77.

Fig. 11 shows the mapping board 82-1, 82-2...8
A data bus 81 to which the arithmetic circuit 703 is connected has a width of 48 bits, and data is read from the microprogram memory 701 and transmitted to the arithmetic circuit 70.
The microprogram given to 3 is horizontal and 63 bits wide.

Then, the 63-bit 1 sent by the host computer 83
The word microprogram is serially transmitted to shift register 715 using load line 85 and converted to parallel data.

The microprogram 701 roughly converted into parallel data by the shift register 715 is sent to the gate buffer 714.
The data is written into the microprogram memory 701 via the microprogram memory 701.

Therefore, even though the arithmetic circuit 703 executes a 63-bit wide microprogram, the data bus 8
1 can use a 48-bit width.

This eliminates the need to expand the data bus 81, making it easier to design and construct the system, and significantly reducing manufacturing costs.

Furthermore, since a microprogram can be loaded into the microprogram memory 701 with any bit width of 63 bits or less, it is also possible to increase the flexibility of the system.

In general, since the only things that need to be added compared to the conventional method are basically the load line 22 and the shift register 715, the mounting space on the board is not restricted, and the manufacturing cost does not increase by 1. Nor.

Here, the mapping board 82-1, 82-2...82-7
When loading the same microprogram to 7, all the mapping boards 82-1.82-2...82-77 receive the sending program, or all the mapping boards 82-1.82- 2...82-77, a method is adopted in which they are designated one after another and the corresponding programs are sent out.

However, the mapping board 82-1, 82-2...8
When it becomes necessary to load a different microprogram to only a portion of the 2-77, the latter method is adopted, and it takes a long time to load the program.

The present invention has been made in view of this situation, and its purpose is to provide a parallel processing device that can efficiently selectively load microprograms as in the above case.

[Means for Solving the Problems] In order to achieve the above object, an apparatus according to the present invention is configured as shown in FIG.

Unit calculation means 11-1, 11-2...11-n in the same figure
performs operations using microprograms at the same time.

Further, the program loading means 12 includes the unit calculation means 11.
-1. Load the microprogram into the designated one among 11-2...11-n.

Then, the load destination specifying means 13 specifies all the unit calculation means 11-1, 11-2...11-n as the load destination of the same program, and then individually specifies the load destination of other programs, according to an external instruction. do.

[Operation] In the present invention, the microprogram is loaded by the load destination specifying means 1.
Unit calculation means 11-1゜11-2... specified in 3.
11-n by the program loading means 12.

And all unit calculation means 11-1.11-2...1
The same microprogram is first loaded into 1-n,
Next, other microprograms are loaded into the individually designated unit calculation means 11-1, 11-2, . . . 11-n.

[Embodiments] Hereinafter, preferred embodiments of the apparatus according to the present invention will be described based on the drawings.

FIG. 2 shows the overall configuration of the embodiment, in which a data bus 81 and a control bus 20 are arranged in parallel.

The display data obtained by the data monitor board 15 of the unit 80 is given to the monitor 16, and the buffer memory board 17 is used for parallel calculations.

Roughly speaking, commands are given from the host computer 83 to the controller board 84 via the command cable 18.

In addition, data way I/F from data way 21-1.21-2 connected to data cable 19-1.19-2
Data from the host computer 83 and other upper side is given to the board 22-1, 22-2, and the host computer 83
Sending microprogram is data way I/F board 2
2-1 and the data bus 81 to the program load control board 23.

In the program load control board 23, data way I/
The microprogram given from the F board 22-1 is converted into serial data, and the program is transferred to the mapping board 82-1.82- via the load line 85 (preferably using the signal line of the control bus 20). 2・
...loaded into 82-77.

The above program loading to the mapping boards 82-1, 82-2...82-77 is performed under the control of the controller board 84, which includes a decoder 30° gate 31 and a 32. Counter 33. Decoder 34, flip-flop 35. A gate buffer 36 is provided.

Among these, the decoder 30 includes a host computer 83
8-bit parallel reset code (code number is 0XFE and OX indicates hexadecimal number), command code, AUX code, source specification code, dest specification code, start code (code number is 0XFE) in the following order:
It is given as shown in figure (A).

In this decoder 30, by applying a reset code, a pulse shown in FIG.

A host computer 83 is installed at the gates 31 and 32.
The strobe pulse of FIG. 4(B) (synchronized with the code data of the host output) is given from the gate 31, and the resulting pulse of FIG. 4(D) is sent from the gate 31 to the 5T of the control bus 20. - Sent on the RESET line.

Furthermore, the gate buffer 36 is opened by the gates 31 and 32 and the flip-flop 35, and the code data at that time is sent to the data bus 81 via the gate buffer 36 as shown in FIG.

Roughly, it is possible to specify the next command code (the memory start address for storing the microprogram) to the decoder 30. In other words, it is possible to specify the microprogram to be loaded.

), the counter 32 counts up and the decoder 34 obtains the pulse shown in FIG. 4(E), which is sent to the ST-MOD line of the control bus 20.

Next, an AUX code is sent to the decoder 30 (the destination for loading the microprogram can be specified. When it is 0-OX4E, the mapping board specified by that code is specified.
In the case of X4F, all mapping boards are designated. ), the pulse shown in FIG. 4(F) is sent to the ST/AUX line of the control bus 20.

When the source specification code (0'X80 specifies the data way I/F board) is given to the decoder 30, the pulse shown in FIG. 3(G) is sent to the 5T-3RC line of the control bus 20. and especially the code 0X4F
When , the pulse shown in the figure (G) is sent to the ST/ALL line, and the mapping board 82-1.
-77 is specified.

In addition, when the decoder 30 headest designation code (program load control board is designated at OXEO) is given, the pulse of FIG.
In particular, when the code 0X4F is given, the pulse shown in FIG.

The input of this dest designation code can be repeated until the input of the start code, and therefore, when the input is repeated, the data of the code and the pulse shown in FIG. 4(H) are sent out.

When the last start code is applied to the decoder 30, the pulse shown in FIG. 4(I) is sent to the 5T-8TART line, and downloading of the microprogram is started.

FIG. 5 shows a flowchart of the processing procedure performed by the program load control board 23, and FIG. 6 explains an example of its operation.

For example, from the host computer 83 to the controller board 84 heliset code = OXFF command code = OX40 AUX code = OX4F source specification code = oxs.

Dest specification code = OX84 Start code = OXFE are given in order, Fig. 6 (A>, (B)).

The pulses of (C), (D>, (E), (F), and (G) are the 5T-RESET line of the control bus 20.

ST-MOD line, 5T-AUX line, 5T-3RC line, 5
It is sent to the T-DST line, 5T-3TART line, and ST/ALL line, respectively.

In that case, connect all the mapping boards 82-1 with the AUX code.
．． 82-2...82-77 is specified as the program load destination, the start address of the program load is specified as address 400 by the command code, and the data way I/F board 22-1 is specified as the sending side by the source specification code. The program load control board 23 is designated as the source board on the receiving side, and the program load control board 23 is designated as the destination board on the receiving side.

Finally, when the pulse shown in FIG. 6 (F) is sent to the 5T-3TAR line, the pulse shown in FIG.
) is given along with the strobe pulse shown in (J) of the same figure.

As described above, all the mapping boards 82-1゜82-2
...The host computer 83 can instruct the loading of the same program to the mapping board 82-77.
-1. ．． When loading a certain program only to 82-77 and loading other programs to all remaining mapping boards 82-2..., all mapping boards 82-1.8
2-2...82-77 is first ordered to load the same program, and then the mapping board 82-1.82-
Loading of other programs only for 77 is sequentially ordered.

In this case, the program to be loaded is specified by the above-mentioned command code, and the load destination is specified by the AUX code.

In the unit 80, a microprogram is sent out from the data way I/F board 22-1 of the source port and taken into the program load control board 23 of the dest board.

Between the data way I/F board 22-1 and the program load control board 23,
, (N>), data (microprogram main body) is sent and received using a 3-wire handshake method,
This transmission and reception is carried out by the control bus 2 using the pulse shown in the same figure (E).
The process starts after the WO2/MOD line of 0 becomes the L level as shown in the figure (H>) (see FIG. 5).

And on the program load control board 23, 1 word 4
Every time 8-bit data is captured twice, they are
It is converted into a 9-DRO 3-bit microprogram, and this microprogram is converted into serial data and sent to the WO2-DT line of the load line 85 as shown in FIG. 6(0).

Further, together with this serial data, the clocks (63 clocks) shown in FIG.

The same figure (Q) after roughly sending serial data and clock.
The pulse of the control bus 20 is WO2-W.
It is sent to the E line.

On the other hand, all the mapping boards 8 specified by the AUX code mentioned above
2-1.82-2...82-77 enters the microprogram download mode (step mode described later) when the WO2/MOD line goes to L level, and in that mode, the serial data on the WO2-DT line is WO2-
It is converted into 63-bit parallel data by the clock on the CK line and loaded into memory.

The level of the *RUN line, whose potential is driven to L level on each board in operation, is monitored at the time of each parallel data reception.

Dataway 1/F that was transmitting this parallel data
While the board 22-1 transmits all data and completes its transmission process, all the mapping boards 82-1.8
2-2...82-77 is completed, and as a result, when it is confirmed by this level monitoring that the potential of the *RtJN line has become H level, the program load control board 23 outputs WO2-MOD. The line is set to H level (see Figure 5).

In Fig. 7, a mapping board 82-1, 82-2...82-
A microprogram read from a microprogram memory 701 (high-speed RAM) is given to a pipeline register 702, and the microprogram is executed by an arithmetic circuit 703 composed of an ALU, memory, etc. executed.

As a result, the mapping board 82-1, 82-2...82-
Parallel computation is performed in step 77, and as a result, line segments of the object contour are extracted.

The read address of the microprogram memory 701 is specified by the output of the sequencer 704.

This sequencer 704 has 5TART input and MODE to AM2910 made by Advance Micro Devices Co., Ltd.
input, 5TEP input is added, MO
, the normal sequencer mode is selected when the DE large input is at H level.

In its normal mode, 5TEP input is ignored and 5TAR
When a pulse is given to the T input, the value given to the 5TART-ADR input is changed to the initial count value = START-A
Sequencer operation with DRx16 is started.

Furthermore, the output data of the pipeline register 702 is lN
When given to the 5T input, counting, jumping, branching, etc. are performed according to the data, and the 5TO
When the data of the P command is given, the sequencer operation is stopped.

Also, when the MODE input is at L level, the Stellar RX16
becomes.

When a pulse is applied to the 5TEP input while operating in this mode, the sequencer output is counted up for each pulse.

When power is applied to the above unit data bus 80,
Downloading of the microprogram is started, at which time the pulse shown in FIG. 6A is sent to the ST-RESET line to reset flip-flops 705, 706, and 707.

And all mapping boards 82-1, 82-2...82-7
7 is specified by the pulse shown in FIG. 6 (G) sent onto the 5T-ALL line, or when the match between the set address of the DIP switch 708 and the address of the data bus 80 is confirmed by the comparator 709, this mapping board is specified, the output of gate 710 is output to flip-flop 7.
The output of flip-flop 707 is applied to gates 711 and 712 with the pulse shown in FIG.

At that time, the response shown in FIG. 6(B) is determined on the ST-MOD line.

The program load control board 23 is designated by the pulse shown in Fig. 6 (E) roughly sent to the 5T-DST line, and the program load control board 23 is then sent to the WO2-MoD line as shown in Fig. 6 (H). Since the MODE input is at L level, the sequencer 704 selects the step mode described above.

Further, the output of the flip-flop 707 is applied to the gate buffer 7714 via the gate 712 on the WO2-MOD line, thereby opening the buffer 7714.

In the shift register 715, the 63-bit serial data shown in FIG. 6 (0) sent to the WO2-DT line is transferred to the WO2-C.
It is converted into parallel data using 63 clocks synchronously sent to the K line, and the 63-bit parallel microprogram obtained by the conversion is applied to the microprogram memory 701 via a buffer 714.

Next, when the pulse shown in FIG. 6 (Q) sent to the WO2-WE line is applied to the gate 711, the output;
Applied to the TEP input.

As a result, the parallel microprogram of the shift register 715 is written in the microprogram memory 701, and the sequencer 704 counts up at the fall of this pulse, and the address output to the microprogram memory 701 is incremented.

However, the gate 716 is opened by the pulse shown in FIG. 6(F) sent to the 5T-3TART line, and the output of the gate 717 is given to the 5TART input of the sequencer 704 via the gate 716 at the level of the WO2/MOD line. , the count up of the sequencer output address is 5T as mentioned above.
This is performed using ART-ADRX16 as the initial value.

The above operations are repeated and the mapping board 82-1゜82-
2...When all the microprograms are downloaded to 82-77 in units of 1 word and 63 bits, WO2-
The MOD line becomes H level as mentioned above, and the sequencer 7
At step 04, the aforementioned normal mode is selected.

The l5TB line of the control bus 20 is connected to the control bus 20.

The RDY line and ACK line are used, and these lines are shown in Figure 6 (L
), (M), and (N) three-wire handshake pulses are sent out.

When the mapping board 82-1, 82-2...82-77 is designated as a source board or a destination board by the 5T-8RC line or 5T-DS king pulse during normal mode, the Flip-flops 705 and 706 operate, a pulse on the 5T-3TART line is applied to the sequencer 704 through the gate 716 opened by the flip-flops 705 and 706, and data transfer is started in a three-wire handshake method.

Therefore, the arithmetic circuit 703 includes a flip-flop 705.
, 706 are applied, and data on the data bus 80 is applied via a flip-flop 718.

The three-wire handshake is driven to the potential of the arithmetic circuit 703, and the mapping boards 82-1, 82-2, . . .
・In 82-77, as with other boards, *STB line, RD
It is pulled up by a resistor along with the Y line and the ACK line.

Rani 1SRJJN line is open collector driver 71
9 drives the open collector driver 719 to an L level potential during board operation, and the open collector driver 719 is controlled by the arithmetic circuit 703.

Under this control, the tRUN line is driven to an L level potential during data transmission/reception processing, and when this processing is quickly completed,
Level driving is completed, and the potential of the IRUN line returns to H level.

Then, when the potential of the *RLIN line returns to the H level and transfer completion is confirmed, the controller board 84 notifies the host computer 83.

Note that if the board designated as the transmitting side is not mounted, the IRUN line will not go to L level, and the controller board 84 will detect the non-mounting of the transmitting side board by monitoring the IRUN line level at the time of board designation. be done.

As mentioned above, 63 transmitted by the host computer 83
The one-bit word microprogram is converted into serial data by the program load control board 23 and sent to the load line 85.

The microprogram is then applied from the load line 22 to the shift register 715 and converted into parallel data.

Furthermore, the microprogram 701 converted into parallel data by the shift register 715 is transferred to the gate buffer 714.
The data is written into the microprogram memory 701 via the microprogram memory 701.

Therefore, even though the arithmetic circuit 703 executes a 63-bit wide microprogram, the data bus 8
1 can use a 48-bit width.

This eliminates the need to expand the data bus 81, making system design and construction easier, and the v! It is also possible to reduce the cost to 44 units.

Furthermore, since a microprogram can be loaded into the microprogram memory 701 with any bit width of 63 bits or less, it is also possible to increase the flexibility of the system.

Roughly speaking, the basic things that should be added to the conventional ones are:
By inputting a predetermined code string from the host computer 83 at the time of system startup, all mapping boards 82-i, 82-2...82-7 with command codes specified
7, the same microprogram with the AUX code specified is first loaded.

Then, the mapping board 82-1 specified by the next code string.
82-2...82-77 is loaded with another program designated by the same code string, and as a result, the microprogram is rewritten only for this individually designated program.

For this reason, the mapping board 82-1, 82-2...82-
When loading a different microprogram into only a portion of the 77, this selective loading can be performed efficiently.

Furthermore, since the controller board 84 manages the loading of the microprogram according to commands from the host computer 83, the host computer 83 does not need to perform any special processing for managing the microprogram. The load can be significantly reduced.

[Effects of the Invention] As explained above, according to the present invention, parts of the same microprogram are loaded into all unit calculation means, and then different microprograms are individually loaded into some of the unit calculation means. Since rewriting is performed, this type of selective program loading can be performed efficiently.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the invention; Fig. 2 is an explanatory diagram of the overall configuration of the embodiment; Fig. 3 is an explanatory diagram of the circuit configuration of the controller board in the embodiment; Fig. 4 is an illustration of the operation of the controller board in the embodiment. FIG. 5 is a flowchart showing the processing procedure of the program load control board; FIG. 6 is a signal waveform diagram explaining an example of the operation of the program control board; FIG. 7 is a circuit diagram of the mapping board in the embodiment; FIG. 8 is an explanatory diagram of the overall configuration of the conventional device, FIG. 9 is an explanatory diagram of the configuration of the mapping board in the conventional device, FIG. 10 is an explanatory diagram of the overall configuration of the proposed device, and FIG. It is an explanatory diagram of the configuration of the board. 719... Open collector driver

Claims (1)

[Claims] A plurality of unit calculation means (11-1, 11-2...11-n) that simultaneously perform calculations by microprograms, and designated unit calculation means (11-1, 11-2...11-n).・・１
A program loading means (12) that loads a microprogram into the microprogram (1-n), and a program loading means (12) that loads a microprogram into the
1-2...11-n) as a load destination for the same program, and then individually specifies a load destination for another program. .