JPH0223423A - Unit arithmetic circuit for parallel arithmetic unit - Google Patents

Abstract

PURPOSE:To improve system performance by converting the microprogram of serial data to parallel data and writing the converted microprogram into a memory. CONSTITUTION:A microprogram is stored into a freely writable memory means 11 and the microprogram red from the means 11 is executed by an arithmetic means 12. The microprogram of serial data is sent to a signal line 13 and the microprogram of the signal line 13 is converted to parallel data by a data serial parallel converting means 14. Further, the microprogram converted to the parallel data by the means 14 is given to a program writing means 15 and the microprogram of the parallel data is written to the means 11. Thus, the microprogram of the bit width not limited to a data bus can be written into the memory and the performance of the system can be improved.

Description

[Detailed Description of the Invention] Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention [Summary] The present invention provides the following features: Performing operations simultaneously in a parallel computing device It pertains to unit arithmetic circuits, and in particular to unit arithmetic circuits whose arithmetic microprograms can be rewritten, and the bit width of the internal data bus connected to the circuit that executes the microprogram and the bit width of the microprogram. The purpose of the present invention is to provide a unit arithmetic circuit that can load a microprogram into memory even if the microprogram is different from the one shown in FIG. arithmetic means for execution; a signal line to which a serial data microprogram is sent; a data serial/parallel conversion means for converting the microprogram on the signal line into parallel data; and a memory means for writing the microprogram converted to parallel data. and a program writing means for writing the program.

[Industrial Application Field] The present invention relates to a unit arithmetic circuit that performs parallel arithmetic operations in a parallel arithmetic device.

JP-A-59-184973, JP-A-60-21818
No. 3, Patent Application No. 1982-258140, Patent Application No. 1983-258
The apparatus shown in No. 8141 and the like is capable of performing parallel calculations for extracting contours of photographed objects.

In each board used for unit operations in these devices, microprograms are loaded into RAM, and those RAM
Parallel operations are performed by simultaneously executing the microprograms read from M.

The microprogram to be loaded into the RAM can be changed arbitrarily, thus increasing the degree of freedom of the device.

Moreover, RAM is a fast memory with low power consumption.
Since it is more suitable than ROM and is easily available, it is advantageous in designing and manufacturing the device.

[Prior Art] FIG. 6 shows a unit 60 that can be used in the above-described apparatus to extract the contour of an object to be photographed, and includes mapping boards 62-1, 62-2, . . . connected to a data bus 61. 62-77
Parallel operations are performed by executing the operations simultaneously.

These calculations are performed by a microprogram, and the microprogram on the host computer 63 communicates with the mapping board 62-1.6 via the data bus 61.
2-2...62-77 is loaded.

Various commands are given from the host computer 63 to the controller board 64 of the unit 60, and the controller board 64 controls the inside of the unit 60.

FIG. 7 shows mapping boards 62-1, 62-2, . The data is written into a microprogram memory 701 composed of a RAM via a gate buffer 714 (three-state buffer).

The microprogram read from the microprogram memory 701 is passed through the pipeline register 702 to the arithmetic circuit 703 (ALU).

(consisting of a memory, etc.), and the arithmetic circuit 703 performs processing according to the microprogram.

Roughly, the output data of the pipeline register 702 is given to the sequencer 704, and the sequencer 704 uses the input data to program the microprogram memory 701.
The read address of is obtained.

[Problems to be Solved by the Invention] Here, since the microprogram is loaded into the microprogram memory 701 via the data bus 61,
The bit width of the microprogram is limited to less than the width of the data bus 61.

Therefore, if the bit width of the data bus 6 is restricted when constructing the system, the bit width of the microprogram is restricted to less than that, making it difficult to further improve the performance of the system.

The present invention has been made in response to the above-mentioned conventional problems,
The purpose is to provide a unit arithmetic circuit that can write a bit-width microprogram in memory that is not limited by the data bus, and that can further improve system performance.

[Means for Solving the Problems] In order to achieve the above object, a circuit according to the present invention is configured as shown in FIG.

A microprogram is stored in the writable memory means 11, and the microprogram read from the memory means 11 is executed by the arithmetic means 12.

A serial data microprogram is sent to the signal line 13, and the microprogram on the signal line 13 is converted into parallel data by the data serial/parallel conversion means 14.

The microprogram roughly converted into parallel data by the data serial/parallel converting means 14 is sent to the program writing means 15.
The parallel data microprogram is written into the memory means 11.

[Operations] In the present invention, the microprogram to be written into the memory means 11 is given from the outside via the signal line 13 in the form of serial data.

The serial data microprogram is converted into parallel data by the data serial/parallel conversion means 14, and the microprogram converted into parallel data is written into the memory means 11 by the program writing means 15.

[Embodiments] Hereinafter, preferred embodiments of the circuit according to the present invention will be described based on the drawings.

FIG. 2 shows the overall configuration of the embodiment, and the unit 60 includes mapping boards 62-1, 62-2...62-7.
7 and controller board 64 together with data way I
/F board 65-1.65-2. Screen control board 6
6, buffer memory board 67, data monitor board 6
8 is provided.

Of these, the buffer 7 memory board 67 is the mapping board 6
2-1, 62-2, .

The data way I/F board 65-1, 65-2 is provided between the data bus 61 and the data ways 20-1 and 20-2, and is used to transfer data between the upper side such as the host computer 63 and the unit 60. Dataway 20 for transfer
-1.20-2 and data way I/F board 65-1
．． 65-2.

Also, the mapping board 62-1, 62-2...62-77
The microprogram to be loaded is provided from the host computer 63 side to the data way I/F board 65-1 via the data way 20-1.

Roughly, this microprogram is arithmetic board control board 6
6 and converted to serial data.

The ram is sent out and the mapping board 62-1, 62-2...
62-77.

Note that commands given to the unit 60 from the host computer 63 are interpreted by the controller board 64,
Control data obtained by the controller board 64 through this interpretation is given to each board via the control bus 21.

FIG. 3 shows a schematic configuration of this embodiment, and as can be understood from the figure and the above description, the unit 60 includes each mapping board 62-1, 62-2...62-77. A load line 22 is provided extending over the load line 22, and the microprogram on the host computer 63 side that is serially sent to the load line 22 is transferred to the mapping board 62-1, 62-2...62-77.
loaded into.

Fig. 4 shows a mapping board 62-1, 62-2...62-
77 is shown.

The data bus 61 to which the arithmetic circuit 703 is connected has a width of 48 bits, and the microprogram read from the microprogram memory 701 and applied to the arithmetic circuit 703 is of a horizontal type with a width of 63 bits.

Therefore, in the arithmetic board control board 66, a 63-bit 1-word microprogram is extracted from 48-bit 2-word data.

Then, the 63 bit 1 sent by the arithmetic board control board 66
The word microprogram is applied from load line 22 to shift register 715 and converted to parallel format.

Furthermore, the microprogram 701 converted into parallel format by the shift register 715 is written into the microprogram memory 701 via the gate buffer 714.

FIG. 5 shows a specific circuit configuration of the mapping board, and the read address of the microprogram memory 701 is designated by the output of the sequencer 704.

This sequencer 704 has 5TART input and MODE to AM2910 made by Advance Micro Devices Co., Ltd.
input, 5TEP input is added, MO
The normal sequencer mode is selected when the DE input is at H level.

In its normal mode, 5TEP input is ignored and 5TAR
When a pulse is given to the T input, the value given to the 5TART-ADR input is changed to the initial count value = START-A
Sequencer operation using DRX16 is started.

Roughly, the output data of the pipeline register 702 is lN.
When applied to the 5T input, counting, jumping, branching, etc. are performed according to the data, and then the lN5T
When the data of the 5TOP instruction is applied to the input, the sequencer operation is stopped.

Further, when the MODE input is at L level, the step mode is selected, and when a pulse is applied to the 5TART input, the value of the sequencer output to the microprogram memory 70''l becomes 5TART-ADRX16.

When a pulse is applied to the 5TEP input while operating in this mode, the sequencer output is counted up for each pulse.

When a reset signal is input from the 5T-RESET line of the control bus 21 at the start of loading the microprogram, the flip-flops 705, 706, and 707 are reset.

And all mapping boards 62-1, 62-2...62-7
7 is specified by a pulse sent to the 5T-ALL line, or the host computer 63 is given via the setting address of the DIR switch 708 and the data bus 61.
When the mapping board is designated by the comparator 709 confirming that the address matches the address of The output of is given to gates 711 and 712.

At that time, the address data of the data bus 61 is transferred to the sequencer 704 through the flip-flop 713 by a pulse given from the ST-MOD line of the control bus 21.
It is applied to the TART-ADR input and the start address is determined.

Further, a pulse sent to the 5T-DST line of the control bus 21 specifies the arithmetic board control board 66 as the load source.

The control bus 2 is controlled by this arithmetic board control board 66.
1's WO2-MOD line becomes L level, which causes M
When the ODE input becomes L level, the sequencer 704 selects the step mode described above.

Furthermore, the output of the flip-flop 707 is applied to the gate buffer 7714 via the gate h712 on the WO2-MOD line which has become L level, thereby opening the buffer 714.

In the shift register 715, the load line 22 WO2-DT
The 63-bit serial horizontal microprogram sent to the WO2-CK line is converted into parallel data using 63 clocks sent synchronously to the WO2-CK line, and the 63-bit parallel microprogram obtained by the conversion is Microprogram memory 701 via buffer 714
given to.

Next, the pulse input from the WO2-WE line is applied to the gate 7.
11, and its output is given to the microprogram memory 701 and the 5TEP input of the sequencer 704.

As a result, the microprogram output from the shift register 715 is written into the microprogram memory 601.

Furthermore, the sequencer 704 performs a count-up at the falling edge of this pulse, and the microprogram memory 704
The address of the output for 1 is incremented.

However, since the gate 716 is opened by the pulse input from the 5T-3TART line and the output of the gate 717 is given to the 5TART input of the sequencer 704 via the gate 716 at the level of the WO2-MOD line, the count up of the sequencer output address is As mentioned above, 5TART-AD
This is done with RXI6 as the initial value.

When the above operations are repeated, the mapping board 62-1.6
2-2...62-77 are sequentially loaded with microprograms in units of 1 word and 63 bits.

After that, when the microprogram has finished loading, W
The O2-MOD line becomes H level, and the sequencer 704 selects the above-mentioned normal mode.

In the normal mode, the dest board is other than the arithmetic board control board 66, and the other boards are designated as the source board or the dest board.

And mapping board 62-1.62-2...62-77
5T-3RC of control bus 21 during normal mode.
DIP switch 70 when designated as source or destination board by pulse on line or 5T-DST line.
8 and comparator 709 cause flip-flop 70
5,706 operates, flip-flop 705,706
A pulse on the 5T-3TART line is applied to the sequencer 704 through the gate 716 which is opened, and data transfer using the 3-wire handshake system is started.

Therefore, the arithmetic circuit 703 includes a flip-flop 705.
, 706 are applied, and data on the data bus 80 is applied via a flip-flop 718.

The 15TB line of the roll bus 20 to the controller 1 connected to the arithmetic circuit 703 is used for the 3-wire handshake.

RDY line and ACK line are used.

For these, an IRUN line is added to the control bus 21, and this tRUN line is driven to the L level potential by the operating boards until their operations are completed.

The *STB line, RDY line, A
The CK line and *RUN line are pulled up by a resistor, and an open collector driver 71 is controlled by an arithmetic circuit 703.
9, it is driven to an L level potential.

Of these, the *RUN line is driven to the L level potential by the operating boards until their operations are completed, so the termination of the participating board designated as the source board or dest board will cause the termination of those boards or third party boards. can be detected by level monitoring.

As described above, in this embodiment, the load line 22 is provided exclusively for loading the microprogram into the microprogram memory 701, and the horizontal microprogram of 63 bits 1 word is executed for unit operations via the WO2-DT line of the load line 22. Circuit mapping board 62-1. ! 32-2・
...Serial transmission to 62-77.

And mapping board 62-1.62-2...62-77
Then, the serial data microprogram is converted to parallel data by the shift register 715, and the microprogram converted to parallel data is converted to 63 bits 1.
It is written into the microprogram memory 701 in units of words.

63 roughly read from the microprogram 701
The bit-width microprogram is read out to the arithmetic circuit 703 via the pipeline register 702, and the data read out during its execution is transferred to the 48-bit wide data bus 61.
is sent from the arithmetic circuit 703 to.

That is, even though the arithmetic circuit 703 executes a 63-bit wide microprogram, the data bus 61
A 48-bit width can be used.

This eliminates the need to expand the data bus 61, making it easier to design and construct the system, and significantly reducing manufacturing costs.

Furthermore, since a microprogram can be loaded into the microprogram memory 701 with any bit width of 63 bits or less, it is also possible to increase the flexibility of the system.

Furthermore, since the only things that need to be added compared to the prior art are basically the load line 22 and the shift register 715, the mounting space on the board is not restricted and the manufacturing cost does not increase.

[Effects of the Invention] As explained above, according to the present invention, a microprogram can be loaded into each unit arithmetic circuit in the form of serial data, so the bit width of the microprogram can be expanded and the bit width of the microprogram can be increased without increasing the data bus. It becomes possible to construct a high-performance parallel processing device at low cost.

Also, since the microprogram is transmitted serially,
The bit width can be changed arbitrarily, thereby increasing the flexibility of the circuit.

Since only a few members need to be added, there is no restriction on the mounting space and no increase in manufacturing costs.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the invention, Fig. 2 is an explanatory diagram of the overall configuration of the embodiment, Fig. 3 is an explanatory diagram of the schematic configuration of the embodiment, Fig. 4 is an explanatory diagram of the schematic configuration of the mapping board, and Fig. 5 is an explanatory diagram of the general configuration of the embodiment. A circuit diagram of a mapping board, FIG. 6 is an explanatory diagram of the configuration of a conventional parallel computing device, and FIG. 7 is an explanatory diagram of the configuration of a conventional example. 21... Control bus, 22... Load line, 60... Unit, 61... Data bus, 62-1.62-2...62-77... Mapping board, 63... Host computer, 64... Controller board, 66... Arithmetic board control board, 701... Micro program memory, 702...
Pipeline register, 703... Arithmetic circuit, 704... Sequencer, 714... Gate buffer, 715... Shift register. Diagram for explaining the principle of the invention Figure l

Claims (1)

[Claims] Writable memory means for storing microprograms (
11), arithmetic means (12) for executing the microprogram read from the memory means (11), a signal line (13) to which the serial data microprogram is sent, and a microprogram on the signal line (13). data serial/parallel conversion means (14) for converting the data into parallel data; and program writing means (15) for writing the microprogram converted into parallel data into the memory means (11).
A unit arithmetic circuit of a parallel arithmetic device, characterized in that it has the following.