JPH02234238A - Execution break control circuit - Google Patents

Abstract

PURPOSE:To attain the follow-up even to a high speed action clock of a CPU by connecting a head fetch signal to the input of a break detecting comparator like the address signal received from the CPU and omitting a gate circuit. CONSTITUTION:A head fetch signal 15 produced by a head instruction detecting part 1A is connected to one of two pieces of input of a comparator 1B. At the same time, an address data bus 11 led from a CPU is connected to the other input of the comparator 1B. The comparator 1B compares the break point information set previously with an input signal and outputs a break detecting signal 12A when the coincident is obtained from the comparison. Thus the inhibition control is possible to a head instruction without using any extra gate circuit after the comparator 1B. Then a break state is detected at a high speed and the follow-up is possible even to a high speed action clock of the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention This invention relates to a microprocessor (cpu) on a device under test.
) in an in-circuit emulator that emulates the program (target program) on the device under test, and in particular relates to a control circuit that prohibits an execution break of only one instruction immediately after the start of execution of the target program. It is. (b) Prior art and problems Next, the configuration of the prior art will be explained with reference to FIG. One of the main functions of in-circuit emulators is the execution break function. This is the detection part 1 as shown in Figure 2.
monitors the instruction fetch address of the target CPU 3, and if it matches a preset break point address, disables the data path buffer 4, disconnects the data bus 13 of the target CPU 3 from the actual machine 5, and executes the break instruction. By enabling the buffer 2B of the insertion section 2, the target CPU
This is a function that causes 3 to read a specific break instruction 2A and causes it to break when an attempt is made to execute the breakpoint instruction. Detection unit 1 detects breakpoints. The break instruction 2A may be IN depending on the type of target CPU 3.
T instructions, TRAP instructions, undefined instructions, etc. are used. Note here that when stopping the Yuichi get program by an execution break, break before executing the instruction at the breakpoint. In other words, after stopping at a breakpoint while running the target program,
Even if you try to run the target program again, it will be re-executed from the address where the breakpoint was set, so you will break again before the target program executes anything. To prevent this from happening, it is necessary to prohibit execution breaks only for one instruction immediately after program execution. One example of conventional techniques for this purpose is a method in which only the first instruction is step-executed when executing a target program, and then RUN is executed. This method has the advantage of being easily implemented using only software, but it has the following problems. (a) The time from the first command execution to the next command execution is long, and it does not operate in real time.
(b) The first executed instruction is not stored in the real-time trace memory. Another conventional technology is one with the circuit configuration shown in Figure 3. Target CPLl3 address/status bus 11
is monitored by comparator IB, and break detection signal 12 is detected.
Give an A. At the same time, the start fetch signal 15 indicating that it is the start instruction fetch cycle immediately after the start instruction detection unit IA"c'RUN is output. The comparator IB is for break detection. Signals 12A...l5 are sent to the gate circuit IC. By inserting the break insertion signal 12B, a break insertion signal 12B that is masked and does not become active in the first fetch cycle is output.The signal 12B controls the break instruction insertion unit 2 and the data path buffer 4 as the enable/dipble control signal 12 in FIG. As an example of the head instruction detection unit IA, the elliptical structure shown in Fig. 4 can be considered.
Latch the UN signal 14 with the flip-flop 1A. At this time, a data strobe signal DS, which indicates that the CPU 3 is executing a bus cycle, is used as a latch clock.
By using the edge after RUN, the first fetch signal can be high for up to one bus cycle immediately after RUN, and can be low for the second and subsequent bus cycles. However, in such a configuration, one more gate passes through the break detection converter IB, which increases the break judgment time by about 10 ns, which reduces the CPU time as shown in the time chart in Figure 5. There is a problem that when the operating clock becomes faster, processing cannot be done in time. Figure 5 is a time chart of Figure 3. Time T in FIG. 5A is the delay time of the converter IB, and time T2 in FIG. 5C is the delay time of the gate circuit IC. Time T3 in Figure 5 is a delay time of the break instruction insertion section 2A, and time T4 in Figure 5 O is a time that is not in time for time T3 in Figure 5. (C) Purpose of the Invention By connecting the head fetch signal to the input of the break detection comparator in the same way as the address signal from the CPU 3, it is possible to omit the gate circuit IC and use the break detection signal as it is as a break insertion signal. Make it.
This eliminates the delay time in the gate circuit IC. (d) Embodiment of the Invention Next, an embodiment of the invention will be explained with reference to FIG. The head instruction detection unit IA is the same as the IA in FIG.
For example, the configuration is as shown in Figure 4. This detection part I
The head fetch signal l5 generated at A is sent to the converter I
Connected to one of the inputs of B. An address/status bus 11 from the CPU 3 is connected to the other input of the comparator IB. Converter IB compares the input signal with breakpoint information set in advance, and if they match, break detection signal 12
Give an A. The signal 12A controls the buffer 2B of the break instruction insertion section 2 and the data path buffer 4 as the enable/disable control signal 12 in FIG. Breakpoint information is set in advance in the comparator IB of FIG. 1, and at that time, the input terminal to which the head fetch signal 15 is connected is set to match "L". As a result, in the first instruction fetch immediately after RUN, the head fetch signal 15 is r H , so even if the address/status bus from the CPU 3 matches the breakpoint condition, it does not match as a whole, and the break detection signal 12
A is not active. After the second fetch, the first fetch signal 15 is r.
l, ”, so the other address/status bus 1
When l matches the breakpoint condition, there is a match as a whole, the break detection signal 12A becomes active, and a break operation occurs. In this way, in Figure 1, the first instruction can be inhibited without placing an extra gate circuit after the comparator IB, so break detection can be performed at high speed, and it can also keep up with the speeding up of the CPU operating clock. can do. (e) Effects of the Invention According to the present invention, the processing time for detecting a breakpoint is shorter than that required for the gate circuit, which increases the processing time, stabilizes the operation, and speeds up the CPU operating clock. ICE can follow suit.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment according to the present invention, FIG. 2 is a configuration illustration of a prior art, and FIG. 3 is a configuration explanatory diagram of another prior art.
FIG. 4 is a block diagram of the head instruction detection unit IA, and FIG. 5 is a time chart of FIG. 3. 1...--Detection section, IA
......Top instruction detection section, 1B...--Comparator, 2...Break instruction insertion section, 3...-
...Target CPU, 4...Data path buffer, 5-...Actual machine, 11...Address/status bus, 12...Enable/day enable, 12A ...Break detection signal, 12
B...Break insertion signal, 13...Data path, 14...RUN signal, 15...
...Start fetch detection signal. Diagram

Claims (1)

[Claims] 1. When the CPU executes a target program according to an instruction from the ICE, detecting that it is the first instruction fetch;
A first instruction detection unit (1A) that outputs a first fetch signal (15)
), and a comparator (1B) that inputs a head fetch signal (15) and an address/status bus from the CPU, compares it with preset breakpoint information, and outputs a break detection signal. circuit.