JPH02235143A - 2n-bit arithmetic circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of operation by dividing one computing element into two computing elements, inputting the upper bit and lower bit of data to respective computing elements and computing two data in parallel. CONSTITUTION:The 2n-bit computing element 3 is divided into an upper n-bit computing element 3-1 and a lower n-bit computing element 3-2 and the carry-in terminals of the computing elements 3-1, 3-2 are connected to each other through a gate 7. In the case of executing the parallel operation of data, the upper n-bit data of two 2n-bit buses are inputted to the computing element 3-1 and lower n-bit data are inputted to the computing element 3-2. At that time, the gate 7 is set up to an inhibition state, alpha bits are shifted by a shifting means 8 and the shifted bits are inputted to a (2n+2alpha)-bit computing element 6. In the case of computing 2n bits, the gate 7 is set up to a through state to inhibit the shifting means 8 from shifting. Since parallel operation can also be enabled, the efficiency can be improved. Provided that (n) is a positive integer.

Description

[Detailed Description of the Invention] [Summary] A 2n-bit arithmetic register that holds data sent from two 2n-bit buses, and a 2n-bit arithmetic register that inputs and calculates the output of each of the arithmetic registers. An arithmetic unit, a 2n-bit sub-accumulator that holds the arithmetic result of the arithmetic unit, and performs an operation by inputting the data held by the sub-accumulator and the data held by the accumulator, and sends the result of the operation to the accumulator. Regarding a 2n-bit arithmetic circuit that has a (2n+2α)-bit arithmetic unit that is held, the purpose of providing an efficient 2n-bit arithmetic circuit that can be performed in parallel when performing operations on n-bit data is to use a 2n-bit arithmetic unit. divided into an upper n-bit arithmetic unit that performs an operation on the upper n bits and a lower n-bit arithmetic unit that performs an operation on the lower n bits, and a carry-out terminal of the lower n-bit arithmetic unit;
The carry-in terminals of the upper n-bit arithmetic units are connected via a gate, and the upper n-bit data of the sub-accumulator is inputted to the (2n+2α)-bit arithmetic unit via a shift means. When performing a 2n-bit operation, the gate is passed through,
When performing n-bit operations without shifting using the shift means, input n-bit data to the upper n bits and lower n bits of the two 2n-bit buses, and disable the gate. state, and the shifting means shifts α bits and inputs the (2n+2α) bits to the arithmetic unit. [Field of Industrial Application] The present invention relates to a 2n-bit arithmetic circuit used in digital signal processing LSIs and the like, which performs both n-bit data arithmetic and 2n-bit data arithmetic.

[Conventional technology]

FIG. 3 is a block diagram of a conventional 16-bit arithmetic circuit.

This arithmetic circuit is designed for 16 bits, and the 16 bit data input from the 16 bit bus 11.12 is selected by the selector 9.10. For example, the data on the bus 11 is input to the 16 bit arithmetic register 1. To, bus l2
The data, is held in the 16-bit operation register 2,
The data is input to a 16-bit arithmetic unit 3 and calculated, and the resulting data is held in a 16-bit sub-accumulator 4.

Subacute. The data held in the mulrator 4 is 24 bits together with the data held in the 24-bit accumulator 5.
The data is input to a bit arithmetic unit 6 and calculated, and the result of the calculation is held in a 24-bit accumulator 5. In this case, the data held in the 24-bit accumulator 5 may become more than 16 bits due to multiple accumulations of 16-bit data, so it is stored as a 24-bit accumulator as shown in (a). , and the arithmetic unit 6 is also a 24-bit arithmetic unit.

[Problems to be Solved by the Invention] However, when performing an operation on 8-bit data using this arithmetic circuit, since the arithmetic circuit is for 16 bits, the upper 8 bits of the 16-bit operation registers 1 and 2, A part that calculates the upper 8 bits of the bit arithmetic unit 3, a part that calculates the upper 8 bits of the 16-bit subachie mulator 4, a part that calculates the upper 12 bits of the 24-bit arithmetic unit 6, and
The upper 12 bits of the bit accumulator 5 are not used, resulting in poor efficiency. An object of the present invention is to provide an efficient 2n-bit arithmetic circuit that can perform arithmetic operations on two n-bit data in parallel when performing arithmetic operations on n-bit data.

[Means to solve the problem]

Figure 1 is a block diagram of the principle of the present invention. As shown in FIG. 1, there is a 2n-bit calculation register 1.2 that holds data sent from two 2n-bit buses, and a 2n-bit calculation register 1.2 that inputs the outputs of each of the calculation registers 1.2 and performs calculations. A bit arithmetic unit 3, a 2n-bit sub-accumulator 4 that holds the operation result of the arithmetic unit 3, and data held by the sub-accumulator 4, (2n+
In a 2n-bit arithmetic circuit having a 2.n + 2α)-bit arithmetic unit 6, the data held in a 2α)-bit accumulator 5 is input, the arithmetic operation is performed, and the result of the arithmetic operation is held in the accumulator 5. The n-bit arithmetic unit 3 is divided into an upper n-bit arithmetic unit 3-1 that performs an operation on the upper n bits and a lower n-bit arithmetic unit 3-2 that performs an operation on the lower n bits. The carry-out terminal of the sub-accumulator 2 and the carry-in terminal of the high-order n-bit arithmetic unit 3-1 are connected via a gate 7, and the data of the high-order n bits of the sub-accumulator 4 is transferred via a shift means 8 to t'. It is arranged to be input to the h (2 n + 2α) bit arithmetic unit 6.

When performing an operation on 2n-bit data, the gate 7 is turned on, and the shift means 8 is not shifted, and a normal 2n-bit operation is performed.

Also, when performing parallel operations on n-bit data, two 2
n-bit data is input to the upper n bits and lower n bits of the n-bit bus, the gate 7 is disabled, and the shift means 8 shifts α bits so that the (
2n+2α) bits are input to the arithmetic unit 6.

[For production]

According to the present invention, in the 2n-bit arithmetic circuit shown in FIG.
When performing parallel operations on bit data, the upper n bits of two 2n-bit buses. The n-bit data is input to the lower n bits, the gate 7 is disabled, and the shift means 8 shifts α bits so that the data is input to the (2n+2α)-bit arithmetic unit 6. Then, the data of the upper n bits and lower n bits of the two 2n-bit buses are held in the upper n bits and lower n bits of the 2n-bit operation registers 1 and 2, respectively, and The data held in the upper n bits is input to the upper n bit arithmetic unit 3-1, and the data held in the lower n bits of the calculation registers 1 and 2 is input to the lower n bit arithmetic unit 3-2. The operation results of the upper n bits of the arithmetic unit 3-1 are held in the upper n bits of the sub-accumulator 4, and the operation results of the lower n bits of the arithmetic unit 3-2 are held in the lower n bits of the sub-accumulator 4. It is held in n bits.

The data held in the lower n bits of the sub-accumulator 4 is transferred to the (2n+2α) bits of the arithmetic unit 6.
The data that is input to the lower (n+α) bits of the arithmetic unit and held in the upper n bits of the sub-accumulator 4 is shifted to the upper α bits by the shift means 8 and becomes (2 n
+2α) bits to the upper (n+α) bits of the arithmetic unit 6, and the lower (n+α) bits of the (2n+2α) bits accumulator 5. Each operation is performed with the data held in the upper (n+α) bits, and the resulting data is stored in the lower (n+α) bits and upper (n+α) bits of the (2n+2α) bit accumulator 5, respectively. Retained. Therefore, two n-bit operations can be performed in parallel.

Of course, when performing a 2n-bint operation in this 2n-bit arithmetic circuit, input 2n-bit data from two 2n-bit buses, set the gate 7 through, and prevent the shift means 8 from shifting. , it becomes a normal 2n-bit arithmetic circuit and can perform arithmetic operations normally. [Embodiment] Fig. 2 is a block diagram of a 16-bit arithmetic circuit according to an embodiment of the present invention, and Fig. 4 shows the luminance of two blocks of 4 x 4 pixels when the luminance of one pixel is represented by 8 bits. It is a diagram showing the number of calculations when calculating the cumulative difference. The difference between FIG. 2 and FIG. 3 is that the 16-bit arithmetic unit 3 is divided into two, an upper 8-bit operator 3-1 and a lower 8-bit operator 3-2, and the lower 8 bits are Arithmetic unit 3-
2 carry-out terminal and upper 8-bit arithmetic unit 3-
When the carry-in terminal of 1 is connected via the AND gate 7 and the upper 8 bits of data of the sub-accumulator 4 are sent to the 24-bit arithmetic unit 6, the selector 8 is used to perform 8-bit arithmetic. , 4 bits are shifted upwards and sent, and when a 16-bit operation is performed, the selector 8 is used to send the data without shifting.

The following explanation will focus on these different points.

When performing operations on 16-bit data, use AND gate 7.
1 level is input as MODE to the selector 8 to make it through, and 1 level is input as MODE to the selector 8 to prevent shifting.

Then, the same operation as explained in the conventional example in Fig. 3 is performed.
Can perform operations on 6-bit data. When performing 8-bit parallel operations, the upper 8 bits of two l6-bit buses,
Input 8 bits of data to each of the lower 8 bits, input O level as MODE to AND gate 7 to disable it, input 0 level as MODE to selector 8, shift by 4 bits to 24 bits. input to the arithmetic unit 6.

Then, the data of the upper 8 bits and lower 8 bits of the two 16-bit buses are held in the upper 8 bits and lower 8 bits of the 16-bit operation registers 1 and 2, respectively. The data held in the upper 8 bits is input to the upper 8 bits arithmetic unit 3-1, and the data held in the lower 8 bits of calculation registers 1 and 2 is input to the lower 8 bits arithmetic unit 3-2. The operation results of the upper 8 bits of the operator 3-1 are held in the upper 8 bits of the sub-accumulator 4, and the operation results of the lower 8 bits of the operator 3-2 are held in the lower 8 bits of the sub-accumulator 4. It is held in 8 bits.

The data held in the lower 8 bits of the sub-accumulator 4 is stored in the lower 12 bits of the 24-bit arithmetic unit 6.
The data input to the bit operation section and held in the upper 8 bits of the sub-accumulator 4 is shifted to the upper 4 bits by the selector 8 and input to the upper 12 bit operation section of the 24-bit operation unit 6. Then, operations are performed on the data held in the lower 12 bits and upper 12 bits of the 24-bit accumulator 5, and each data of the operation result is stored in the lower 12 bits of the 24-bit accumulator 5.
bit. Each is held in the upper 12 bits.

Therefore, two n-bit operations can be performed in parallel. This held state is as shown in Fig. 2(a), and 4
Bit shifting is . This is to allow the number of bits to increase by carrying the result of accumulation. Therefore, as shown in Fig. 4 (A) and (B), when the luminance of one pixel is represented by 8 bits, the cumulative value of the difference in luminance of each pixel of two blocks consisting of 4 × 4 pixels is calculated. When calculating the case using a 16-bit arithmetic circuit, the conventional 1
A comparison between the case of using a 6-bit arithmetic circuit and the case of using a 16-bit arithmetic circuit of the present invention will be explained.

When using a conventional 16-bit arithmetic circuit, as shown on the left side of Figure 4, the difference in brightness of each pixel consisting of 8 bits is calculated and accumulated, so 16 calculations are required. However, when using the 16-bit arithmetic circuit of the present invention, as shown on the right side of FIG. This means that only one calculation is required, which increases the calculation speed. [Effects of the Invention] As explained in detail above, according to the present invention, when n-bit operations are performed using a 2n-bit arithmetic circuit, the operations can be performed in parallel, thereby improving efficiency. .

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. Figure 2 is a block diagram of a 16-bit arithmetic circuit according to an embodiment of the present invention. Figure 3 is a block diagram of a conventional 16-bit arithmetic circuit. Figure 4 is a block diagram of a 16-bit arithmetic circuit. When the brightness of is expressed in 8 bits, 4×
FIG. 7 is a diagram showing the number of calculations when calculating the cumulative difference between the tan levels of two blocks of 4 pixels. In the figure, 1.2 is a 2n-bit arithmetic register, a 16-bit arithmetic register, 3 is a 2n-bit arithmetic unit, a 16-bit arithmetic unit, 3-1
is an arithmetic unit for upper n bits, an arithmetic unit for upper 8 bits, and 3-2 is an arithmetic unit for lower n bits. Lower 8-bit arithmetic unit, 4 is a 2n-bit sub-accumulator, 16-bit sub-accumulator, 5 is a (2n+2α)-bit accumulator. 24-bit accumulator, 6 is a (2n+2α) bit arithmetic unit, 7 is a gate, and gate, 8 is a shift means. 9.10 is a selector, and 11.12 is a 16-bit bus. 24-bit block diagram of the present invention 1 (2) Block diagram of the 7th generation numerator subordinate I{column digit/hexagram operation circuit Figure 3 Two east cells of the 4 Gift + force calculation number of hours diagram

Claims (1)

[Claims] 2n-bit arithmetic registers (1, 2) each holding data sent from two 2n-bit buses, and inputting the respective outputs of the arithmetic registers (1, 2). A 2n-bit arithmetic unit (3) that performs calculations, a 2n-bit sub-accumulator (4) that holds the calculation results of the arithmetic unit (3), and data held by the sub-accumulator (4);
A (2n+2α) bit arithmetic unit (2n+2α) which performs calculations by inputting data held in an n+2α) bit accumulator (5) and causes the accumulator (5) to hold the calculation result.
6), in which the 2n-bit arithmetic unit (3) is an upper n-bit arithmetic unit (3-1) that performs an operation on the upper n bits, and a lower n-bit arithmetic unit (3-1) that performs an operation on the lower n bits. It is divided into arithmetic units (3-2), and the carry-out terminal of the lower n-bit arithmetic unit (3-2) and the carry-in terminal of the upper n-bit arithmetic unit (3-1) are connected via a gate (7). The data of the upper n bits of the sub-accumulator (4) is inputted to the (2n+2α)-bit arithmetic unit (6) via the shift means (8), and 2n-bit arithmetic is performed. When performing an n-bit operation, the gate (7) is set to pass and the shift means (8) does not shift, the upper n bits and lower n bits of two 2n-bit buses n-bit data is input into each of the gates (7) and the gate (7) is inhibited, and the shift means (8) shifts α bits to the (2n+2)
A 2n-bit arithmetic circuit characterized in that input is input to an α)-bit arithmetic unit (6).