JPH0223640A - Resin sealed type semiconductor device - Google Patents

Abstract

PURPOSE:To make recessed parts provided in a sealing resin decrease stress which is exerted to a semiconductor chip and improve the reliability of a resin sealed type semiconductor device by providing recessed parts at least on an upper surface of a sealing resin substance which lays the semiconductor chip in the resin as well as at least at a part of the inside part above the semiconductor chip. CONSTITUTION:A semiconductor chip 10 which is 8mm square is connected to a lead frame 30 electrically through a bonding wire 20 and recessed parts 53 and 63 are formed by machining at parts located in the inside regions of a sealing resin 40. Each recessed part is dimensioned as 7.5X7.5X1mm and it reduces the volume of the sealing resin 40 on the semiconductor chip 10 to half approximately. Such a state of the sealing resin allows shrinkage stress of the above sealing resin 40 on the semiconductor chip 10 to be relieved and the movement volume of wiring in the square of the semiconductor chip 10 is reduced to one-thirds. The decrease in this stress prevents the semiconductor chip from being damaged. It is needless to say that the above mentioned effect is obtained if the recessed part is mounted at least on the chip side, that is, on the upper surface of the chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to a resin-sealed semiconductor device with improved reliability.

[Conventional technology]

In semiconductor devices where semiconductor chips are sealed with resin,
The semiconductor chip and the sealing resin body in which it is embedded,
They often separate due to stress, creating a gap between them. This stress is caused by the difference in thermal expansion coefficient between the semiconductor chip and the sealing resin, curing shrinkage of the sealing resin, and the like. The above-mentioned gap promotes the penetration of water from the outside, corrodes the metal material portion within the semiconductor chip, and causes early deterioration of the device.

Therefore, a device as described in Japanese Patent Publication No. 60-8627 has been proposed for the purpose of alleviating the stress between the semiconductor chip and the sealing resin and preventing the two from peeling off. FIG. 5 shows this conventional device, with 10
is a semiconductor chip, which is electrically connected to a lead frame 30 via a bonding wire 20, and is coated with a sealing resin 4.
It is buried in 0.

Here, grooves 55 and 65 for stress absorption were formed on the upper or lower surface of the sealing resin so as to surround the semiconductor chip 10 when viewed from the plane.

That is, the main purpose of this prior art is to reduce the stress exerted by the semiconductor chip 10 by shrinking the sealing resin region on the outside of the semiconductor chip 10 in FIG. 5(a).
The grooves 55 and 65 provided on the outside of the buffer absorb the heat, thereby improving reliability.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration the case where the integration of semiconductor devices progresses, semiconductor chips become larger, and elements and wiring become finer.
For example, there has been a problem in that there are insufficient measures against deformation of wiring, disconnection, short circuit, cracking or deformation of insulating film, and the like. Further, in the conventional technology, since a groove or a recess is provided on the outer periphery of the semiconductor chip, there is a problem in that the ability of the sealing resin to support the lead frame is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor device that has a high lead frame support capacity and reduces damage to semiconductor chip constituent materials.

[Means to solve the problem]

The above object is achieved by a resin-sealed semiconductor device characterized in that a recess is provided in at least a portion of the inner side of the semiconductor chip on at least the upper surface of the sealing resin body in which the semiconductor chip is embedded.

In the present invention, the recess may have a shape such as a groove, a recess, a hole, or the like. Furthermore, the cross-sectional shape of the groove may be of any shape, such as square, U-shaped, or V-shaped. Further, the recess may be provided at least on the upper surface of the sealing resin body, that is, on the side where the semiconductor chip is mounted, but it may be provided on both the upper surface and the lower surface.

[Effect]

When a large semiconductor chip is encapsulated with resin, the stress acting on the semiconductor chip is reduced by the encapsulation resin located on the top surface of the semiconductor chip, rather than the shrinkage stress caused by the encapsulation resin on the outside of the semiconductor chip, which was considered in the conventional technology. The contribution of the stress exerted on the chip as it tries to shrink is rather large.

Therefore, by providing a recess in a portion of the sealing resin on the inside of the semiconductor chip when viewed from the plane, the stress in the sealing resin located on the upper surface of the semiconductor chip is alleviated, and the shrinkage stress acting on the semiconductor chip is reduced. damage to the semiconductor chip is prevented, and the supporting capacity of the lead frame is not reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
FIG. 1(a) is a plan perspective view of a resin-sealed semiconductor device, and FIG. 1(b) is a sectional view taken along line X-X' shown in FIG. 1(a). Reference numeral 10 indicates an 8M1 square semiconductor chip, which is electrically connected to the lead frame 30 via the bonding wire 20 and has a recess 53 in a portion located inside the sealing resin 40.
was formed by machining. This recess had a length and width of 7.5 mm and a depth of 1 mm, and the volume of the sealing resin 40 on the semiconductor chip 10 was approximately halved. According to this embodiment, the shrinkage stress of the sealing resin 40 on the top surface of the semiconductor chip is alleviated, and the wires at the 10 corners of the semiconductor chip, which were conventionally deformed and moved by 3.8 μm toward the center, are reduced to 1.3 μm. We were able to reduce the amount of movement by 1/3. By reducing this stress, damage to the semiconductor chip is prevented. In this embodiment, the recesses 53 and 63 are provided on both the upper and lower surfaces of the sealing resin, but it goes without saying that the effects of the present invention can be obtained by providing recesses at least only on the chip side, that is, on the top surface.

FIGS. 2, 3 and 4 each show other embodiments of the invention.

FIG. 2 is a plan view of a resin-sealed semiconductor device in which a groove 52 for stress relaxation is provided above a portion of a corner of a semiconductor chip. The stress acting on a semiconductor chip increases as it moves away from the center of the chip, and is greatest at the periphery of the chip, especially at the corners. Therefore, by providing a groove on at least a portion of the chip corner as in this embodiment, it was possible to reduce the chip breakdown failure rate due to stress.

FIG. 3 shows a resin-sealed semiconductor device in which grooves 51 and 61 are formed in the inner region of the semiconductor chip when viewed from the plane direction. FIG. 3(,) is a plan view thereof, and FIGS. 3(b) and 3(Q) are sectional views taken along lines y-y' and xx' in FIG. 3(,), respectively. According to this embodiment, the shrinkage stress of the sealing resin on the upper surface of the semiconductor chip is alleviated.

FIG. 4 shows a sealing resin plate 44 for the semiconductor device shown in FIG.
This shows the device with the attached. It has a structure in which holes 45 are provided in the sealing resin 40. According to this embodiment, in addition to the effect of reducing the stress acting on the semiconductor chip, there are effects such as increasing the mechanical strength of the sealing resin and improving moisture resistance.

Note that the groove shape provided in the sealing resin of the present invention does not necessarily have to be the same as that shown in the above embodiments;
No matter what shape it is, such as a V-shape or a V-shape, the effect will not be lost. The same applies to recesses and holes in addition to grooves.

〔Effect of the invention〕

As described above, according to the present invention, the stress acting on the semiconductor chip can be reduced by the grooves, recesses, holes, etc. provided in the sealing resin located on the semiconductor chip, and the damage to the semiconductor chip caused by this stress can be reduced. This has the effect of improving the reliability of resin-sealed semiconductor devices.

Further, in the present invention, since the groove, recess, hole, etc. are provided near the center of the sealing resin body, the problem of deterioration of the lead frame supporting ability of the sealing resin is reduced.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 1(b) is a sectional view thereof. 2, 3, and 4 are a plan view and a cross-sectional view of a resin-sealed semiconductor device according to another embodiment of the present invention, and FIG. 5 (
a) is a plan view of a conventional resin-sealed semiconductor device; FIG. 5(b) is a plan view of a conventional resin-sealed semiconductor device;
) and FIG. 5(c) are sectional views thereof. 10... Semiconductor chip 20... Bonding wire

Claims (1)

[Claims] 1. A resin-sealed semiconductor device, characterized in that a recess is provided in at least a portion of the inner side of the semiconductor chip on at least the upper surface of a sealing resin body in which a semiconductor chip is embedded.