JPH0223653A - integrated circuit - Google Patents
integrated circuitInfo
- Publication number
- JPH0223653A JPH0223653A JP63174118A JP17411888A JPH0223653A JP H0223653 A JPH0223653 A JP H0223653A JP 63174118 A JP63174118 A JP 63174118A JP 17411888 A JP17411888 A JP 17411888A JP H0223653 A JPH0223653 A JP H0223653A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- resistance
- writing
- current
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体素子を集積化して構成された集積回路
に関し、特にプログラム素子の集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit configured by integrating semiconductor elements, and particularly to an integrated circuit of a program element.
［従来の技術１ 本発明に於けるプログラム素子の従来例を第３に示す。[Conventional technology 1 A third conventional example of the program element according to the present invention is shown below.
３０１の半導体基板上に基板とは異種導電型の拡散層３
０３を設け、その両端に電極３０４．３０５を形成する
。この時３０５の電極と３０３の拡散層の間に３０６の
アモルファスシリコンをはさむ。本素子の動作は、両電
極間に電圧、電流を印加し、印加前の数ＭΩ〜数ＧΩの
抵抗を数百Ω近傍程度まで低下させることでプログラム
するものである。この素子を集積化するには、従来第２
図の回路構成が用いられてきた。２０１は印加のための
電源、２０２は、スイッチング素子で、書き込み、非書
き込みを選択するスイッチであり、２０３が本プログラ
ム素子である。A diffusion layer 3 having a conductivity type different from that of the substrate is formed on the semiconductor substrate 301.
03, and electrodes 304 and 305 are formed at both ends thereof. At this time, amorphous silicon 306 is sandwiched between the electrode 305 and the diffusion layer 303. The operation of this element is programmed by applying a voltage and current between both electrodes and reducing the resistance from several MΩ to several GΩ before application to around several hundred Ω. In order to integrate this element, conventional
The circuit configuration shown in the figure has been used. 201 is a power supply for application, 202 is a switching element that selects writing or non-writing, and 203 is a main programming element.
［発明が解決しようとする課題］
プログラム素子の性能としては低電圧、低電流印加でよ
り低抵抗化が得られるものの方がよい。[Problems to be Solved by the Invention] As for the performance of the program element, it is better to have a program element that can achieve lower resistance with low voltage and low current application.
実験結果から書き込み後の抵抗値は主として書き込み電
流に対して強く依存していることがわかった。したがっ
て第２図の回路ではスイッチ素子２０２のオン抵抗によ
って書き込み電流が規制されるため、書き込み後の低抵
抗化に限界があった。The experimental results showed that the resistance value after writing strongly depends mainly on the writing current. Therefore, in the circuit shown in FIG. 2, since the write current is regulated by the on-resistance of the switch element 202, there is a limit to how low the resistance can be after writing.
また２０２のオン抵抗を下げるためには、−１１９的に
集積回路の集積度を犠牲にする必要があった。Further, in order to lower the on-resistance of 202, it was necessary to sacrifice the degree of integration of the integrated circuit by -119.
［課題を解決するための手段］
本発明はかかる課題を解決するために概プログラム素子
と並列にコンデンサーを接続するものである。[Means for Solving the Problems] In order to solve the problems, the present invention connects a capacitor in parallel with the general programming element.
［実 施 例１
本発明の実施例を第１図に示す。１０１は印加電圧、電
流発生のための電源、１０２は選択スイッチ素子、１０
４が概プログラム素子である。[Example 1 An example of the present invention is shown in FIG. 1. 101 is a power supply for applying voltage and current generation; 102 is a selection switch element; 10
4 is a general program element.
本発明は、１０３のコンデンサーを１０４に並列に図の
如く接続するものである。このコンデンサーは、半導体
基板上の拡散容量や、配線と基板間の容量、二層配線間
の容量等によって形成される。In the present invention, a capacitor 103 is connected in parallel to a capacitor 104 as shown in the figure. This capacitor is formed by the diffusion capacitance on the semiconductor substrate, the capacitance between the wiring and the substrate, the capacitance between the two-layer wiring, and the like.
［発明の効果１
第１図かられかるように、書込み時には、１０２の選択
スイッチがオンし、１０４のプログラム素子が書き込み
開始するとともにコンデンサー１０３に電荷が充電され
る。但しこの時には、１０２のオン抵抗のため過大な電
流を１０４に供給することができず１０４の低抵抗化に
限界がある。[Effect of the Invention 1] As can be seen from FIG. 1, during writing, the selection switch 102 is turned on, the program element 104 starts writing, and the capacitor 103 is charged with electric charge. However, at this time, an excessive current cannot be supplied to 104 due to the on-resistance of 102, and there is a limit to how low the resistance of 104 can be made.
次に１０２がオフした瞬間１０３への充電がストップし
、１０３の電荷が１０４を通じて放電される。この時に
は、スイッチ素子を通じていないために、１０４に過大
電流を流すことができ、瞬間的に１０４を所望の値まで
低抵抗化できる。Next, the moment 102 turns off, charging to 103 stops, and the charge in 103 is discharged through 104. At this time, since the switching element is not passed through, an excessive current can flow through 104, and the resistance of 104 can be instantaneously lowered to a desired value.
第１図は、本発明を示す集積回路の配線例を示す図。
第２図は、従来例を示す集積回路の配線例を示す図。
第３図は、本発明に於けるプログラム素子の構造断面図
。
以上
出願人 セイコーエプソン株式会社FIG. 1 is a diagram showing an example of wiring of an integrated circuit according to the present invention. FIG. 2 is a diagram showing an example of wiring of an integrated circuit showing a conventional example. FIG. 3 is a cross-sectional view of the structure of the program element according to the present invention. Applicant: Seiko Epson Corporation
Claims (1)
プログラム可能な素子を集積化した集積回路に於いて、
概プログラム素子と並列にコンデンサーを接続させたこ
とを特徴とする集積回路。In integrated circuits that integrate programmable elements by applying voltage and current to amorphous silicon,
An integrated circuit characterized by having a capacitor connected in parallel with a programming element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174118A JPH0223653A (en) | 1988-07-12 | 1988-07-12 | integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174118A JPH0223653A (en) | 1988-07-12 | 1988-07-12 | integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223653A true JPH0223653A (en) | 1990-01-25 |
Family
ID=15972956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63174118A Pending JPH0223653A (en) | 1988-07-12 | 1988-07-12 | integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223653A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010109338A (en) * | 2008-09-30 | 2010-05-13 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device |
| JP2010267368A (en) * | 2009-04-17 | 2010-11-25 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device |
| KR20110081983A (en) | 2008-09-19 | 2011-07-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor devices |
| JP2011233221A (en) * | 2010-04-09 | 2011-11-17 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device and semiconductor device |
-
1988
- 1988-07-12 JP JP63174118A patent/JPH0223653A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110081983A (en) | 2008-09-19 | 2011-07-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor devices |
| US8822996B2 (en) | 2008-09-19 | 2014-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US9735163B2 (en) | 2008-09-19 | 2017-08-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2010109338A (en) * | 2008-09-30 | 2010-05-13 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device |
| US8344435B2 (en) | 2008-09-30 | 2013-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device |
| JP2010267368A (en) * | 2009-04-17 | 2010-11-25 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device |
| US8964489B2 (en) | 2009-04-17 | 2015-02-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device capable of optimizing an operation time of a boosting circuit during a writing period |
| JP2011233221A (en) * | 2010-04-09 | 2011-11-17 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device and semiconductor device |
| JP2012195050A (en) * | 2010-04-09 | 2012-10-11 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP2015079974A (en) * | 2010-04-09 | 2015-04-23 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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