JPH0223664A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0223664A JPH0223664A JP17412988A JP17412988A JPH0223664A JP H0223664 A JPH0223664 A JP H0223664A JP 17412988 A JP17412988 A JP 17412988A JP 17412988 A JP17412988 A JP 17412988A JP H0223664 A JPH0223664 A JP H0223664A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- semiconductor device
- manufacture
- ion implantation
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 title claims description 4
- -1 oxygen ions Chemical class 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明はトレンチ構造ＭＯ８ＬＳＩのＳＯ工槽構造化為
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a manufacturing method for structuring an SO trench structure MO8LSI.
［従来の技術］
従来、ＭＯＳ ＬＳＩのＳＯ工槽構造化してはＳｉ基
板表面、平面への酸素イオン打込みによる［発明が解決
しようとする課題］
しかし、上記従来技術によると、最近のＭＯ８ＬＳＩの
トレンチ・ゲート化あるいはトレンチ・キャパシタ化に
よる高集積化には、薄いＳ１膜内にはトレンチ・ゲート
やトレンチ・キャパシタを製作することが全く出来ない
と云う課題があった本発明はかかる従来技術の課題をな
くシ、トレンチ・ゲートやトレンチ・キャパシタを用い
たＭＯＳ ＬＳＩのＳＯ工化を可能とする新しい製造
方法を提供する事を目的とする。[Prior art] Conventionally, the SO trench structure of MOS LSI has been achieved by implanting oxygen ions into the surface or plane of a Si substrate.・In order to achieve high integration through gate formation or trench capacitor formation, there was a problem in that it was completely impossible to fabricate a trench gate or trench capacitor in a thin S1 film.The present invention solves this problem with the prior art. The purpose of this invention is to provide a new manufacturing method that enables SO processing of MOS LSI using trench gates and trench capacitors.
［課題を解決するための手段］
上記課題を解決するために、本発明は半導体装置の製造
方法に関し、Ｓｉ基板表面からはトレンチが形成され、
該トレンチの側壁に酸素イオンあるいは窒素イオンのい
ずれかあるいは双方をイオン打込みし、いわゆるＳＯ工
溝構造なす手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a method for manufacturing a semiconductor device, in which a trench is formed from the surface of a Si substrate,
Oxygen ions, nitrogen ions, or both are ion-implanted into the side walls of the trench to form a so-called SO trench structure.
［実施例コ 以下、実施例により本発明を詳述する。[Example code] Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示すトレンチ構造へのＳＯ
工槽構造適用示す要部の断面図である。FIG. 1 shows an embodiment of the present invention in which SO to a trench structure is
FIG. 3 is a cross-sectional view of the main parts showing the application of the construction tank structure.
すなわち、３１基板１の表面から、ホト・リソグラフィ
ーとドライ・エツチングによりトレンチ部２を形成し、
酸素イオン打込みを例えば２００ＫｅＶで１０１８／、
ｉ 程度打込み角度を変えて行なう事により０．５μ
ｍ厚さ程度のイオン打込み層３と、［１１μｍ厚さ程度
のＳ１膜４を少くともトレンチ部２内に形成し、前記イ
オン打込み層５はアニール処理により酸化膜層となし、
ＳＯ工溝構造少くともトレンチ内に形成する事ができる
。That is, a trench portion 2 is formed from the surface of the substrate 1 by photolithography and dry etching,
For example, oxygen ion implantation is performed at 200 KeV at 1018/,
0.5μ by changing the driving angle by about i
an ion implantation layer 3 with a thickness of about m and an S1 film 4 with a thickness of about 11 μm are formed at least in the trench portion 2, the ion implantation layer 5 is made into an oxide film layer by annealing treatment,
The SO trench structure can be formed at least within the trench.
もし、トレンチ部２外の表面、平面に予じめ酸化膜を形
成して置くと、イオン打込み層６０表面を酸化膜内に閉
じ込める事ができると共に、本例の如き場合にはＳ１膜
４のトレンチ部２外の部分のみ後程酸化処理して平面部
は酸化膜のみとなりトレンチ内のみＳＯ工溝構造なす事
ができる。If an oxide film is formed in advance on the surface or plane outside the trench portion 2, the surface of the ion implantation layer 60 can be confined within the oxide film, and in a case like this example, the S1 film 4 can be Only the portion outside the trench portion 2 is oxidized later, so that the plane portion is only an oxide film, and an SO trench structure can be formed only inside the trench.
この様にして形成されたトレンチＳｏ工構造はトレンチ
・ゲー）ＭＯＳ ＦＥＴのゲート部や、トレンチ・キ
ャパシタのキャパシタ部として用いる事が出来、とりわ
けトレンチ・キャパシタをダイナミックＲＡＭの製作の
場合の如く、２個並べて形成する場合にトレンチ・キャ
パシタ間の結晶欠陥によって誘起されるリーク電流によ
る情報消えの現象を、イオン打込み層６の絶縁膜化によ
る素子間分離が完全に行なうことによるリーク電流防止
効果による情報消え現象の、防止を計ることができる。The trench structure formed in this way can be used as the gate part of a trench MOS FET or the capacitor part of a trench capacitor. Information disappears due to leakage current induced by crystal defects between trenches and capacitors when they are formed side by side, but the leakage current prevention effect due to complete isolation between elements by making the ion implantation layer 6 into an insulating film prevents information loss. It is possible to prevent the disappearance phenomenon.
［発明の効果］
本発明により、トレンチ構造ＭＯ８ＬＳＩのＳＯ工溝構
造化計ることができ、ＭＯＳ ＬＳＩの高集積化、高
性能化を計ることができる効果がある。[Effects of the Invention] According to the present invention, it is possible to create an SO trench structure in a MO8LSI with a trench structure, and there is an effect that it is possible to achieve higher integration and higher performance of a MOS LSI.
第１図は本発明の一実施例を示すトレンチ構造のＳＯＩ
化を示す要部の断面図である。
１・・・・・・・・・Ｓ１基板
２・・・・・・・・・トレンチ部
３・・・・・・・・・イオン打込み層
４・・・・・・・・・＄１膜
２トレン牛壱Ｐ
以上FIG. 1 shows an SOI with a trench structure showing one embodiment of the present invention.
FIG. 1...S1 substrate 2...Trench section 3...Ion implantation layer 4...$1 film 2 Train Gyuichi P and above
Claims (1)
側壁に酸素イオンあるいは窒素イオンのいずれかあるい
は双方をイオン打込みし、いわゆるＳＯＩ（Ｓｉｌｉｃ
ｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）構造となす事を特徴
とする半導体装置の製造方法。A trench is formed from the surface of the Si substrate, and oxygen ions, nitrogen ions, or both are ion-implanted into the sidewalls of the trench to form a so-called SOI (Silicon
1. A method for manufacturing a semiconductor device, characterized in that the semiconductor device has an on-on insulator structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17412988A JPH0223664A (en) | 1988-07-12 | 1988-07-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17412988A JPH0223664A (en) | 1988-07-12 | 1988-07-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223664A true JPH0223664A (en) | 1990-01-25 |
Family
ID=15973164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17412988A Pending JPH0223664A (en) | 1988-07-12 | 1988-07-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223664A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0623381A (en) * | 1992-02-07 | 1994-02-01 | Ebara Infilco Co Ltd | Aerobic biological filter bed type treatment method and apparatus |
| WO1998044687A1 (en) * | 1997-03-31 | 1998-10-08 | Hitachi, Ltd. | Modem using capacitive insulating barrier, insulating coupler, and integrated circuit used in the modem |
| US5943589A (en) * | 1997-01-30 | 1999-08-24 | Nec Corporation | Method of fabricating semiconductor device with a trench isolation |
-
1988
- 1988-07-12 JP JP17412988A patent/JPH0223664A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0623381A (en) * | 1992-02-07 | 1994-02-01 | Ebara Infilco Co Ltd | Aerobic biological filter bed type treatment method and apparatus |
| US5943589A (en) * | 1997-01-30 | 1999-08-24 | Nec Corporation | Method of fabricating semiconductor device with a trench isolation |
| WO1998044687A1 (en) * | 1997-03-31 | 1998-10-08 | Hitachi, Ltd. | Modem using capacitive insulating barrier, insulating coupler, and integrated circuit used in the modem |
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