JPH033272A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

FIG. 9 is a cross-sectional view showing a conventional semiconductor device, in which (1) is a silicon substrate, (2) is a channel doped layer for VYS control, and (3) is a silicon substrate formed by implantation. Source and drain impurity diffusion layers, (4
) is a gate oxide film, (5) is a gate electrode, (6) is an insulating film between the eyebrows, and (7) is an AL wiring.

[Problem to be solved by the invention]

Since the conventional semiconductor device is constructed as described above, there is a problem that it is difficult to planarize the gate electrode because it is located on the silicon substrate.

This invention was made to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor device that can be planarized.

[Means to solve the problem]

The semiconductor device according to the present invention has a gate 'ai formed in a silicon substrate.

[Effect]

In the semiconductor device according to the present invention, since the gate electric field is formed within the silicon substrate, the semiconductor device can be planarized.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional view of a semiconductor device, and Figures 2 to 8 are cross-sectional views showing the steps of the manufacturing method of the semiconductor device shown in Figure 1. In Figure 0, (1) is a silicon substrate, and (2) is a v0 control (3) is the channel doped layer implanted for the purpose, (3) is the source and drain impurity diffusion layer formed by implantation, (4)
) is a gate oxide film, (5) is a gate oxide film, (6) is an insulating film between eyebrows, (7) is an AL wiring, and (8) is a resist.

Next, the silicon substrate (11) is etched to form a trench groove (Figure 2) using a pattern using a resist, the manufacturing method of which will be explained with reference to FIGS. A channel doped layer (2) for VTH control is formed by implantation (Fig. 3). A rotational implantation is performed on the pattern of the trench groove resist (8) to form an impurity diffusion layer (3) in the source and drain regions ( (Figure 4).A gate oxide film (4) is formed using the resist pattern of the trench groove.
Figure 5). A gate electrode film (4) is formed on the entire surface, anisotropic etching is performed by dry etching after battening with a resist (8) (FIGS. 6 and 7), and finally a glabellar insulating film (6) is formed. pattern after Jung source
Forming the AL wiring (7) in the drain part (Fig. 8) [Effects of the Invention] As described above, according to the present invention, since the gate electrode is formed in the silicon substrate, there is an effect that the semiconductor device can be planarized. .

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIGS. 2 to 8 are sectional views showing a manufacturing flow for forming the semiconductor device of FIG. 1, and FIG. 9 is a sectional view showing a conventional semiconductor device. FIG. 2 is a cross-sectional view showing a semiconductor device. In the figure, (1) is the silicon substrate, (2) is the channel doped layer, (3) is the source and drain impurity diffusion layer, (4) is the gate oxide film, (5) is the gate electrode, (6) is
is an interlayer insulating film, and (7) is AL! i! Line (8) is a resist. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A semiconductor device characterized by having electrodes formed within a silicon substrate.