JPH02236657A - Information processing system - Google Patents

Abstract

PURPOSE:To prevent the throughput of a master processing unit from being lowered by storing instruction information arriving from the master processing unit while a slave processing unit performs a processing into an independent memory means provided separately under the management of the slave processing unit different from a buffer memory means for processing. CONSTITUTION:The partial area of the memory means 14 to store the processing result of an execution means is used as a memory to store the instruction information, namely, it is provided separately from the buffer memory means in parallel, and an instruction information transfer control means 12 supplies and stores the instruction information supplied from the master processing unit while the execution means performs the processing to the memory means 14. In the case of completing the execution of the execution means at a state where the instruction information is stored in the memory means 14, the oldest instruction information stored in the memory means 14 is transferred to the buffer memory means, and the next processing is executed. Thereby, a processing instruction can be transferred from the master processing unit to the slave processing unit even while the slave processing unit executes the processing without lowering the throughput of the master processing unit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing system having a master processing unit and a slave processing unit that performs only a part of the processing operations. The present invention is suitable for application to graphic processing systems such as design/manufacturing systems and CG (computer graphics) systems.

[Prior Art] For example, in a CAD/CAM system, a central processing unit (CPU) serving as a master processing unit executes design and manufacturing processing through interaction with an operator, for example.
In a CG system, a CPU performs graphic processing through interaction with, for example, an operator. During the execution of such original processing, when a processing step is reached where the operator wants to know the processing details, the graphical output is displayed on the display device. Generally, in order to not reduce the processing power of the CPU even when outputting graphics, the CPU is
An image control device (slave processing unit [-
) controls the graphic output operation.

In other words, the CPU provides drawing commands that instruct drawing shapes such as circles and straight line segments, and data groups related to the drawing commands (
For example, data regarding the center coordinates and radius for a circle drawing command, data regarding the position such as start point coordinates and end point coordinates for a straight line segment drawing command, display color data for the figure part, etc.) are sent to the image control device 2. When the output is finished, the next process is executed immediately regardless of the display output state.

In the image control device 2, an input drawing command and a data group related to the command (hereinafter collectively referred to as drawing information) are stored in an input buffer circuit 3, and an image calculation circuit 4 is stored based on the stored drawing information. performs color gradation imparting processing, pixel expansion processing (in the case of 1"l tiA command, expands to pixels on the circumference or pixels within the circumference), etc., and gives the calculation results to the display memory device W5 and stores them. and display it on the display device 6.

However, the time it takes for the image control device 2 to finish processing one cat drawing command is relatively long compared to the processing speed of the CPU, and while one drawing command is being executed, the next drawing command is executed. C}. ) Often output from U1. CI-) Even if U1 tries to generate the next fuT image command, unless the image control device 2 accepts it, the CPUI cannot proceed to the next process, and the image $1
The advantage of having separate control device 2 is halved. Therefore, conventional image control devices 2 have been proposed that can accept subsequent drawing commands even while a certain drawing command is being processed.

FIG. 3 is a professional diagram showing such a conventional example (refer to the document "Nikkei Electronics Books, Microphone Port Processor Peripheral LSIJ, Published by Nikkei McGraw-Hill, October 1984, ppl 94-195").

In FIG. 3, the input/output circuit 3 of the image control device 2 includes a first-in first-out (FIFO) memory section 3a having, for example, about 20 stages, which sequentially stores drawing information from the CPU 1.
, an instruction register section 3bl that stores drawing instructions related to instruction processing being executed by the image calculation circuit 4, and
It is composed of a plurality of data register sections 3b2 that store data groups related to the instruction processing being executed.

Here, even if the image calculation circuit 4 is given other drawing information from the CPUI during calculation processing using the drawing information stored in the instruction register section 3b1 and data register section 3b2, it will not be stored in the FIFO memory section 3a. CPU
It is possible to accept drawing information from I, thereby preventing the processing of the CPU 1 from being stopped. Note that if the drawing information is stored in the FIFO memory section 3a at the stage where the arithmetic processing being executed is completed, the next drawing information is transferred from the FIFO memory section 3a to the instruction register section 3bl and the data register section 3b2. Then, the image calculation circuit 4 immediately proceeds to the next calculation process.

The problem that this invention tries to solve! However, in reality, the image control device 2 is composed of an integrated circuit such as an LSI, and a large portion of the structure is devoted to the image calculation circuit 4, etc., so that the size of the FIFO memory section 3a is small. Therefore, much drawing information from the CPU 1 cannot be stored. In particular, some drawing information includes a lot of data, and the FIFO memory unit 3a stores drawing commands and data without distinguishing between them. Most of the capacity of the FIFO memory unit 3a is used, and subsequent drawing information from the CPUI is often not accepted.

This inconvenience can be solved by increasing the capacity of the FIFO memory section 3a, but as mentioned above, there are restrictions on the LSI chip. Furthermore, even if the capacity of the FIFO memory section 3a is increased, depending on the graphic processing system to which the image control device 2 is applied, the FIFO memory section 3a may be small in size; It is useless to apply the FIFO memory section 3a.

That is, in the configuration of the image control device 2 shown in FIG. 3, the degree of freedom as a system is reduced because drawing information is kept on standby.

Therefore, a graphic processing system as shown in the block diagram of Figure 4 has been proposed in the magazine "Nikkei Elec 1.
Ronix 4 February 1987, no. 415, ppl3
3-149).

In this conventional example, the input buffer circuit of the image control device 2 includes an instruction register section 3cl that stores drawing instructions related to the instruction processing that the image processing circuit 4 is currently executing, and an instruction register section 3cl that stores drawing instructions related to the instruction processing that the image processing circuit 4 is currently executing. It consists of a plurality of data register sections 3C2 that store such data groups, and any drawing information that is generated afterwards and cannot be stored in these register sections 3cl and 3c2 is stored in the memory 1a of the CPUI. It is.

In this conventional example, the CPUI processes as shown in the flowchart of FIG. 5 to control the transfer of drawing information or the storage of the drawing information in the memory 1a.

During the processing of the main routine, when it becomes necessary to transfer a drawing command, the drawing processing routine is called (step 100). Determine whether the device 3 is executing arithmetic processing (
Step 101). If it is not being executed, the drawing command and data group are output to the image control device 2 and the process returns to the main routine (step 102).On the other hand, if it is being executed,
The interrupt process is set to be executed when the busy signal becomes insignificant, and then the drawing command and data group to be output are stored in the memory 1a, and the process returns to the main routine (steps 103 and 104).

After that, when the image control device 2 finishes the arithmetic processing being executed and makes the busy signal insignificant and an interrupt occurs, the CP
UI calls interrupt handling routine (step 10)
5》. As a result, the drawing command and data group stored in the memory 1a are retrieved and transferred to the image control device 2,
Return to the main routine (steps 106, 107).

In this conventional example, since the memory 1a is used, a large amount of drawing information can be stored. but,
When the next drawing command and data group are generated while the image control device 2 is executing arithmetic processing, the storage processing in the memory 1a and the subsequent interrupt processing are performed as follows: C }) U
1 must execute, the image control device 2 of the drawing information
Many processing steps are required for the transfer to the CPU, which reduces the advantage in terms of processing ability of the CPU that the image control device 2 is provided separately from the CPU.

The present invention has been made in consideration of the above points, and it is possible to
Information that allows processing instructions to be transferred from the master processing unit to the slave processing unit I even while the slave processing unit is executing processing, and that there is less restriction on the number of processing instructions to be transferred while the slave processing unit is executing processing. The aim is to provide a processing system.

[Means for Solving the Problems] In order to solve the problems, the present invention includes a master processing unit and a slave processing unit, and the slave processing unit executes instructions from the master processing unit. A slave processing unit in an information processing system in which other instructions may arrive even during execution of the slave processing unit was configured using the following means.
That is, the slave processing unit includes an execution means for executing instructions, a buffer memory means for storing information about the instruction being executed, and a buffer memory means for storing the processing results executed by the execution means. and memory means for storing information.

Further, while the execution means is not executing, the instruction information given from the master processing unit is given to the buffer memory means, and while the execution means is executing, the instruction information given from the master processing unit is given to the memory means. The instruction information transfer control means is provided for transferring the oldest instruction information stored in the memory means to the buffer memory means when execution of the execution means ends while the instruction information is stored.

[Operation] In the slave processing unit, the execution means executes an instruction according to the instruction information stored in the buffer memory means.

Instruction information given from the master processing unit while the execution means is not executing can be immediately stored in the buffer memory means, and the instruction information transfer control means causes the incoming instruction information to be stored in the buffer memory means. On the other hand, while the command means is being executed, new command information cannot be stored in the buffer memory means, since the command information in the buffer memory means is used. Furthermore, if the slave processing unit 1. does not accept command information from the master processing unit, the processing capacity of the master processing unit will be reduced.

Therefore, a part of the memory means that stores the processing results of the execution means is used to store the instruction information, that is, it is provided separately and in parallel with the buffer memory means, and the instruction information transfer control means is used to store the processing results of the execution means. The instruction information given from the master processing unit is given to the memory means for storage, and when the instruction information is stored in the memory means and the execution of the execution means is finished, the most stored in the memory means is stored. The old instruction information is transferred to the buffer memory means to execute the next process.

[Example] Hereinafter, an example in which the present invention is applied to a graphic processing system will be described in detail with reference to the drawings. Here, FIG. 1 is a block diagram showing the overall configuration of this embodiment, FIG. 6 is a block diagram showing the detailed configuration of the image control device, and FIG. 7 is a diagram showing switching contents of the path selector section. , FIG. 8 is a flowchart showing the drawing command transfer process executed by the CPU of this system.

In FIG. 1, the CPUIO outputs drawing information (a drawing command and a data group related to the drawing command) to the image control device 11 when drawing is required during processing, and in this embodiment, As will be described later, since the image control device 11 does not fail to accept drawing information,
A structure for storing drawing information in internal memory is not provided.

The image control device 11 has a transfer control circuit N12 and an image calculation circuit 1.
3, and CI) calculates the drawing information given from the UIO and converts it into display information and stores it in the display memory device i.
Output to f 1 4. Thus, the display information stored in the display memory device 14 is stored in the display device it.
15 and is displayed.

In this embodiment, the drawing information output by the CPUIO while the image calculation circuit 13 is performing calculations is stored in a part of the area 14a of the display memory device 14. That is, the display memory device 14 is
It is divided into a display information area 14b for storing display information and a drawing information area 14a for storing drawing information, and is used as if there were two memory devices. Actually - Hee,
The area 14b required to store display information is a part of the capacity of the display memory device 14, and there is a free space that can store a lot of drawing information.

The display information area 14b of the display memory device 14 is
It is accessed by the image calculation circuit 13 and display device 15 of the image control device 11 , and the program information area 14 a of the display memory device 14 is accessed by the transfer control circuit 12 of the image control device 11 . That is, in this embodiment, the transfer control circuit 12 is connected to the image calculation circuit 13.
Control is performed so that drawing information from the CPUIO can be accepted even when the CPU IO is executing calculations.

When the transfer control circuit 12 receives drawing information from the CPUIO when the image calculation circuits i/8 1 3 are not executing calculations, the transfer control circuit 12 directly provides the drawing information to the image calculation circuit 13 . Furthermore, when the image calculation circuit 13 is executing calculations, the transfer control circuit 12 receives drawing information from the UIO and stores it in the drawing information area 14a of the display memory device 14. Further, when the image calculation circuit 13 finishes the calculation, the transfer control circuit 12 transfers the oldest drawing information stored in the drawing information area 14a to another drawing information stored in the drawing information area 14a. The information is read out and given to the image calculation circuit 2813 to perform calculations.

Next, the configuration and operation of the transfer control circuit 12 will be explained with reference to FIGS. 6 and 7.

In FIG. 6, the transfer control circuit 12 includes the image calculation circuit 1
3 includes an instruction register section 20 and a data register section 21 for storing drawing commands and data groups being executed.

Internal data bus B1 for these register units 20, 21, and system bus B2 connected to CPUIO
and the drawing information area 14a of the display memory device 14.
The path selector section 22 performs connection switching with the memory data bus B3 connected to the memory data bus B3. Path selector section 22
is controlled by the transfer publication control unit main body 23. The transfer control section Honkyu 23 selects the path selector section 22 based on the busy signal BSY given from the image calculation circuit 13 and the first match/mismatch signal C1 given from the address control section 24 that controls the address for the drawing information area 14a. control.

The address control section 24 includes a start address register section 25 that stores the start address SA of the drawing information area 14a, an end address register section 26 that stores the end address EA of the drawing information area 14a, and a readout section 25 that stores the start address SA of the drawing information area 14a. A read address generation unit 27 that stores the address RA and a write address W for the drawing information area 14a.
A write address generation section 28 that stores A, and a first coincidence detection section 29 that detects coincidence and mismatch between the read address RA and the write address WA and outputs a first coincidence and mismatch signal CI to the transfer control section main body 23. , a second match which detects a match or mismatch between the end address EA and the read address RA, or a match or mismatch between the end address EA and the write address WA, and outputs a second match or mismatch signal C2 to the transfer control unit main body 23. The detection unit 30 selects either the read address RA or the write address WA and prints the drawing information area 14a.
and an address selector section 31 that outputs an address to an address bus BA connected to the address bus BA. Here, the first
The fact that the match detection unit 29 detects a match between the read address RA and the write address WA means that the read address RA
The purpose of this is to detect a situation in which the write address WA has caught up with the write address WA, and to detect whether all the drawing information in the drawing information area t4a has been read out.

Further, the second coincidence detection section 30 detects whether the terminal address EA and the read address RA match or do not match, or c.
Detecting a match or mismatch between A and the write address WA involves detecting whether it is necessary to return the read address RA or the write address WA from the end address EA to the start address SA.

In the above configuration, in the transfer control unit main body 23, as shown in the first column of FIG.
If there is a mismatch between A and the write address WA, the internal data bus B1 and the memory data bus B3 are connected by the path selector section 22, and then the read address RA at that time is incremented and the address selector section 31 is applied to the drawing information area 14a through the drawing information area 14a to cause the drawing information to be read out and transferred to the instruction register section 20 and the data register section 21, and to cause the image calculation circuit 13 to execute calculations on the new drawing information. In this case, after confirming that the second match/mismatch signal C2 indicates that the read address rtA is not the end address EA, the read address generator 2
The read address RA in 7 is incremented. Note that when the read address RA is the end address EA, the start address SA stored in the start address register section 25 is loaded into the read address generation section 27 and output.

Depending on the processing shown in the first column, the busy signal BSY
Since this represents the calculation state, the process proceeds to the third book or the fourth shelf, which will be described later.

In addition, as shown in the second column of FIG.
If the match/mismatch signal C1 indicates that the read address RA and write address WA match (there is no stored drawing information that has not been processed), the internal data bus B1 and system bus 132 are passed. Selector section 2
2, and the drawing information from the (,r) UIO is transferred to the instruction register section 20 and the data register section 21.
3 to perform calculations on the new drawing information. Through the processing shown in the second column, drawing information is given to the image calculation circuit 13 to start calculation processing, and the busy signal B
When SY represents the calculation state, the process proceeds to column 3a or 4, which will be described later.

In addition, the transfer control unit main body 23 is connected to the third column and the fourth column in FIG.
As shown in the column, if the busy signal BSY indicates a bad operation state, the system bus B2 and memory data bus B3 are connected to the path selector unit regardless of whether the first match/mismatch signal C1 matches or does not match. 22, and thereafter, the write address WA at that time is given to the drawing information area 14a via the address selector section 31, and the CPU
When drawing information arrives from IO, the drawing information area 14
a so that it can be stored immediately.

When drawing information arrives from the CPUIO in this state and is stored in the drawing information area 14a, a control signal is given from the display memory device 14 to the transfer control unit main tree 23. confirms that the second match/mismatch signal C2 indicates that the write address WA is not the end address EA, and increments the write address WA in the write address register section 28. In addition, if the terminal address is EA,
The start address SA stored in the start address register section 25 is loaded into the write address generation section 28.

Even if the processing shown in the third column and 4a is performed, the processing in the third column and the fourth column will continue to be executed until the image calculation circuit 13 finishes the calculation processing, and the processing in the third column and the fourth column will be continued. When the signal BSY indicates a non-operation state, the process proceeds to the 18th or second column.

Therefore, according to the above-described embodiment, the memory section (14a> for storing the drawing information received from the CPUIO during the operation of the image operation circuit 13 is provided in parallel with the instruction register section 20 and the data register section 21, and Memory section (14
Write address WA and read address R for a)
Since A is circulated, a lot of drawing information can be stored on the image control device 11 side, and the CPU
There is no restriction on the processing of O.

In other words, (j) the UIO checks the status of the image control device 11 when the need to transfer a drawing command arises and calls the drawing processing routine during processing of the main routine, as shown in FIG. The drawing processing routine can immediately transfer the drawing information without having to do so or store the drawing information in the internal memory, and the main routine can be returned immediately (steps 200 and 2).
01). Further, according to the embodiment described above, the display memory device 14 serves as a drawing information memory associated with the image control device 11.
Since the free space is used, the memory can be used effectively and a large amount of drawing information can be stored. That is, more containers can be used than by providing memory in the image control device 11. moreover,
By varying the start address SA and the end address EA, the storage capacity of drawing information can be arbitrarily varied, and from this point of view as well, the effective utilization of the memory is achieved.

In the above-described embodiment, the present invention is applied to a graphic processing system, but the present invention can also be applied to other information processing systems. That is, a master processing unit I and a slave processing unit are provided, and the slave processing unit 1 executes instructions from the master processing unit, and other processing instructions arrive even during processing. It can be applied to certain systems.

[Effects of the Invention] Therefore, according to the above-described embodiment, the slave processing unit stores the instruction information received from the master processing unit during processing in a separate buffer memory means under the control of the slave processing unit different from the processing buffer memory means. Since the processing results are stored in an independent memory means, it is possible to store a lot of instruction information that is not being executed on the slave processing unit side, and the processing power of the master processing unit can be used for instruction transfer processing. It is possible to obtain an information processing system that does not cause low power consumption.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the overall configuration of an embodiment in which the present invention is applied to a graphic processing system, Fig. 2 is a block diagram showing the overall configuration of a conventional system, and Figs. 3 and 4 are respectively related to the conventional system. FIG. 5 is a flowchart showing the drawing information transfer process executed by the CPU of the conventional system in FIG. 4, and FIG. 6 shows the detailed configuration of the image control device in the above embodiment. Block diagram shown,
FIG. 7 is a diagram illustrating poor operating conditions in relation to control signals, and FIG. 8 is a flowchart illustrating drawing information transfer processing executed by the CPU of the system of the embodiment. 10... CPU, 11... Image control device, 12...
・Transfer control circuit, 13... Image calculation circuit, 14...
Display memory device, 14a... drawing information area,
15...Display device. An overall block diagram of the graphic processing system according to the embodiment ▲ Fig. I 12 An auxiliary block diagram of the conventional example of the image control device (1) Fig. 3 An overall block diagram of the conventional graphic processing system λ item Fig. 2 2'7'rJ7 diagram (2) of a conventional example of an image control device

Claims (1)

[Claims] A master processing unit and a slave processing unit are provided, and the slave processing unit executes an instruction from the master processing unit, and other instructions arrive even during execution processing. In an information processing system, the slave processing unit has an execution means for executing an instruction, a buffer memory means for storing instruction information being executed, a processing result executed by the execution means, and a part of the slave processing unit. memory means for storing unexecuted instruction information in an area; and a memory means for supplying instruction information given from the master processing unit to the buffer memory means while the execution means is not executing; When the instruction information given from the master processing unit is given to the memory means and the execution of the execution means is completed while the instruction information is stored in the memory means, the oldest instruction stored in the memory means An information processing system comprising: command information transfer control means for transferring information to the buffer memory means.