JPH02236736A - Digital input circuit - Google Patents

Abstract

PURPOSE:To improve reliability for input data by holding the input data sequentially at two buffer registers by a clock with a cycle almost equivalent to the time constant of a filter circuit, and outputting data in which coincidence is detected when coincidence detection is performed at a comparator as effective data. CONSTITUTION:A digital signal is inputted via the filter circuit 1, and is held sequentially at the buffer register 3 and the buffer register 4 cascade-connected to the buffer register 3 corresponding to the clock of constant cycle. The clock in this case is provided with the cycle almost equivalent to the time constant of the filter circuit 1. And the identity of both data held at both buffer register 3 and 4 is judged at the comparator 5. When coincidence is obtained in both data, the data in the buffer register 4 is sent out to a CPU side as the effective data by opening a gate 6. Thereby, it is possible to heighten the reliability for the input data handled by a data processor.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to improve the reliability of input data by treating an undefined area at a change point of input data as invalid data in a digital signal input circuit. , a buffer register for holding input digital data, a second buffer register for holding the output of the buffer register, and a buffer register having a period approximately equal to the time constant of a filter circuit provided on the input side of the puffer register. It includes a sampling clock circuit that generates a clock, and a comparison circuit that detects a match between the outputs of the two buffer registers, and uses the clock to sequentially hold human data in both the buffer registers, and when a loss is detected in the comparison circuit. This is configured by outputting the data in which the one loss was detected as valid data.

[Industrial application field]

The present invention is based on Digi. The present invention relates to digital signal input circuits, and particularly to digital input circuits that prevent erroneous data input at changing points of input information in an input/output (I/O) section of a data processing device using a computer.

In telecontrol systems and telemeter systems that collect external data from multiple locations, ``ζ'' collects digital data obtained from sensors, such as rainfall amount and wind speed, to a master station through slave stations, and then processes it using a data processing device using a computer. Necessary data processing is performed, but in this case, the reliability of input data handled by computers, etc. is strongly required. In such a data device, if the digital information read by the central processing unit (CPU) via the I/O unit is parallel data, and changes in data at the sensor occur asynchronously, the data may vary depending on the timing of data capture. Since this method captures changing points in the data, it may result in incorrect data input. In this case, if the human information is, for example, numerical information (IllCBCD code), incorrect data input may affect the results of data processing, leading to serious trouble.

Therefore, there is a need for a digital input circuit that can prevent erroneous data input at changing points of input digital information. [Prior Art] FIG. 4 shows an example of the configuration of a conventional digital input circuit, and FIG. 5 shows its operation in a time chart.

At the time of access from the CPU (not shown), the address comparator 2 receives an address I word from the CPU, a read signal (
A set signal (b) to the buffer register 3 is generated when the internal address is compared with the internal address in response to the al and SET signals. On the other hand, digital input data D.
-D, , pass through a filter circuit 1 with a time constant t, and noise in the input data and chatter of the relay contacts are removed. The output of the filter circuit 1 is read into the buffer register 3 according to the set signal Tb).

When the input data changes from 8 to B, an unstable time region X corresponding to the time constant L of the filter circuit occurs at the point of change. Therefore, when the set signal (b) is generated in this area, the data "X" at the change point is set in the buffer register 3, and therefore the data read from the buffer register 3 to the CPU is the data "X". B
The data that should be "X" changes to the incorrect data "X". Conventionally, as a countermeasure against such incorrect data input, the method shown in Figure 5 (
As shown in 1), the CPU reads the data output as it is, compares it with the previous value, and determines whether the difference is within a predetermined value to determine whether or not the data is incorrect; If it is determined that the data is incorrect, the CP
U was planning to re-read the target digital input circuit.

Another method is to add a BUSY signal as part of the digital input data without indicating the data change point, and as shown in FIG. 5(2), the set signal (
If the BUSY signal is in the on state when bl occurs, the CPU reads this information and re-reads the target digital input circuit.

[Problem to be solved by the invention]

In the former method, in which the CPU judges erroneous data in the digital input circuit, there is a problem in that the load on the CPU side becomes heavy and the processing capacity decreases.

In addition, in the latter method, which indicates the data change point to the CPU using the BUSY signal, it is necessary to have a function to generate and add the BUSY signal on the input data supply side.
There is a problem in that not all input data has a BUSY signal added to it. The present invention aims to solve the problems of the prior art as described above, and adds a signal indicating valid data on the human input data supply side without reducing the processing capacity of the CPU in the digital input circuit. The purpose is to make it possible to output only valid data to the CPU without any need.

[Means to try to solve the problem]

The data input circuit of the present invention has a buffer register 3, . It is equipped with a second buffer register 4, a sampling clock circuit 7, and a comparator circuit 5, and uses the clock of the sampling clock circuit 7 to sequentially hold input data in both buffer registers 3 and 4, and to compare the data. When the circuit 5 detects one loss, the data for which this match is detected is output as valid data.

Here, the buffer register 3 holds input digital data.

The second buffer register 4 is the second buffer register 3.
It holds the output of

The sampling clock circuit 7 generates a clock having a period approximately equal to the time constant of the filter circuit 1 provided on the input side of the buffer register 3.

Comparison circuit 5 detects whether the outputs of both buffer registers 3.4 match.

[For production]

A digital signal is inputted through a filter circuit 1, and is sequentially held in a buffer register 3 and a second buffer register 4 following it in response to a clock of a constant period. The clock in this case has a period approximately equal to the time constant of the filter circuit 1.

The data held in both buffer registers 3.4 are then compared in a comparison circuit 5 to see if they are the same data.

In this case, the sampling timings of both data in the buffer registers 3 and 4 are shifted by a time approximately equal to the indefinite region generated at the output of the filter circuit 1 due to the data change point that occurs on the input data supply side.
If a data change point is sampled, the data in both buffer registers will not be the same. Therefore, since the gate 6 is closed by outputting to the comparator circuit 5, the data in the buffer register 4 is not outputted and becomes invalid data.

On the other hand, if both data are the same data, it is not a change point, and therefore the gate 6 is opened and the data in the buffer register 4 is sent to the CPU side as valid data.

In this way, in the digital input circuit of the present invention, erroneous data at a data change point that occurs on the input data supply side is discarded as invalid data and is not input to a data processing device such as a computer that collects data. It becomes possible to increase the reliability of input data handled by the device.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which the same parts as in FIG. 4 are designated by the same numbers, 4 is a buffer register, 5 is a comparison circuit, 6 is a bus output gate, and 7 is a sampling clock. The circuits 8 and 9 are AND circuits, and 10 is an inverter.

Moreover, FIG. 3 is a time chart showing the signals of each part in the circuit of FIG. 2. Address comparator 2 is accessed by CPU.
is the address signal, read signal and SIE from the CPU.
It compares with the internal address according to the T signal, and when they match, generates an enable (ENB) signal (al).When the sampling clock circuit 7 receives the END {3 (ill), time constant L of l
The clock signal is output with a value close to .

On the other hand, when the comparator circuit 5 receives the ENB signal (+1) and the condition of ■≠■ is satisfied between the output ■ of the buffer register 3 and the output ■ of the buffer register 4, it generates an output (dl). As a result, the sampling clock (b) is applied to the buffer register 3.4 via the AND circuit 8.The buffer register 3.4 sets the data.At this time, the buffer register 4 is the same as the buffer register 3. Since the output data (2) of the buffer register 3 is set at the set timing, the data (2) delayed by one clock is output as shown in the time chart of FIG.

The comparator circuit 5 compares the data with the data (2) and generates an output (C) when the condition (10) of (1) is satisfied.

This opens bus output games 1-6 and outputs the data ([
1 is output on the CPU bus. At this time, the output ((+)
is turned off and the output of the sampling clock (b) from the AND circuit 8 is stopped, so the buffer preregister 3.4
The data of does not change. Next, a response (AKI) signal (c) is generated from the AND circuit 9 by the output (C) and E N D (, tq (a)) and sent to the CPU. Thereby, the CPU reads data. When the read signal of the CPU is turned off due to the completion of reading, the ENB signal ta+ from the address comparator 2 is turned off, and the AK! signal (C1 is turned off, and the ENB signal is given to the Bats 1 register 3 via the inverter 10. As a result, the buffer register 3 is reset.

This allows us to take the condition ζ≠■, so
Output (Cl is turned off, data output (f) is completed, and a series of CPU read accesses is completed.
Output (dl turns on and waits for CPU access.

In this way, when reading data from the CPU, data is sampled at a fixed cycle, and the data before and after one clock has passed. If the data is the same for two consecutive clocks, it is considered valid data. If the data does not become the same due to the filter undefined area of the input data, the data is not output as invalid solution data, so only correct data can be output to the CPU.

(Effects of the Invention) As explained above, in the present invention, data is sampled at a certain period when reading the CPU, and data is considered valid only when the same data is detected over a continuous period. , the data in the anxiety region at the change point of the input data is not output as invalid data.

Therefore, according to the digital input circuit of the present invention, the reliability of data is improved, the load on the CPU is reduced, and addition of functions such as BUSY signal generation on the input data supply side is unnecessary, and the data processing device etc. It greatly contributes to improving confidence.

3.4...Bazza register 5... Comparison circuit 6...Bus output gate 7...Sampling clock circuit 8.9...AND circuit 10...Inverter

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing various signals in the circuit of FIG. 2.
FIG. 4 is a diagram showing a 41)T configuration example of a conventional digital input circuit, and FIG. 5 is a time chart showing the operation of the circuit shown in FIG. 4. l...filter circuit, 2...address converter patent applicant: Fujitsu Co., Ltd. agent, patent attorney, Kugoro Tamamushi (other name) Figure 2 shows the arithmetic structure of the present invention. Time chart showing various signals in the circuit

Claims (1)

[Claims] Buffer registers (3
), a second buffer register (4) that holds the output of the buffer register (3), and a second buffer register (4) having a period approximately equal to the time constant of the filter circuit (1) provided on the input side of the buffer register (3). A sampling clock circuit (7) that generates a clock, and a comparison circuit (5) that detects a match between the outputs of the buffer registers (3) and (4), and includes a sampling clock circuit (7) that generates a clock; ),
In (4), the input data can be held sequentially,
A digital input circuit characterized in that when the comparison circuit (5) detects a match, the data in which the match is detected is outputted as valid data.