JPH0456592A - Information collection system - Google Patents

Abstract

PURPOSE:To collect the same information for many times by providing an input port through which a signal latched in a latch circuit is collected. CONSTITUTION:When an event signal 41 is active, since a flip-flop(FF) 40 is reset, a Q output 42 is kept to a low level. When a CPU accesses an output port 10, a clock pulse 11 is produced, a register(REG) 30 latches information and when the event signal 41 is active, a Q output 42 of the FF 40 goes to a low level and when the event signal 41 is not active, the output goes to a high level. The CPU collects the information for many times by reading the content of the REG 30 via an input port 20. When the CPU accesses the output port 10 and a clock pulse 11 is caused, FFs 40, 50, 60 and the REG 30 latch new information. Thus, the reliability of information collection is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information collection method for collecting information on one or more functional blocks connected to a CPU via a bus.

[Conventional technology]

Traditionally, this type of information collection method captures events that occur one after another in chronological order, and after collecting information once, it is necessary to distinguish whether the event has newly occurred by the time the next time the information is collected. Although it is necessary to clear the information after collecting it, generally a signal indicating the event is held as soon as the event occurs, and a circuit is used that clears the signal at the same time as collecting the information.

FIG. 2 is a block diagram showing an example of a conventional information gathering method.

For example, when an event a occurs and the event a signal 71 becomes active, the flip-flop 70 is reset and the Q output cuff 2 of the flip-flop 70 is held at a LOW level and is input to the input port 20. CPU is input port 2
When 0 is read, the flip-flop 70 is reset by the input port read signal 22, and the Q output cuff 2 of the flip-flop 70 goes to HIGH level, so that the information is cleared by one read.

[Problem to be solved by the invention]

In systems that require reliability of information, it is necessary to read it two or three times because reading it once is not reliable, but in the conventional information collection method described above, the signal is cleared at the same time as information is collected. Therefore, the disadvantage is that the same information can only be collected once.

[Means to solve the problem]

The information collection method of the present invention includes a holding circuit that holds a signal indicating that a certain event has occurred according to a clock, and a CPU.
an output port that generates one pulse of the clock that determines the holding timing by accessing the holding circuit; and an input port that collects the signal held in the holding circuit, and the holding circuit is provided with an output port that generates one pulse of the clock that determines the timing of holding. When the signal is held in the flip-flop, when the CPLI accesses the output port and a clock pulse comes,
This held signal is sent from the flip-flop to a register, and the signal is held in the register until the next clock pulse comes by accessing the CPtJ or the output port, and the CPU transmits the signal via the input port. The information is collected from the register using the register.

〔Example〕

Next, the present invention will be explained with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of the information collection method of the present invention.

For example, when event a occurs and the event a signal 41 becomes active, the flip-flop (hereinafter referred to as FF) 40 is reset, so the Q output 42 of the FF 40 is held at a LOW level. When the CPU outputs an output port address to the address bus 12 and accesses the output port 10, a pulse corresponding to the pulse of the output port ride signal 13 is generated in the clock 11, and at the same time, information is held in the register (hereinafter referred to as REG) 30. Q output 42 of FF 40 is event a signal 41
If the event a signal 41 is active, it becomes a LOW level, and if the event a signal 41 is not active, it becomes a HIGH level. The CPU can collect this information any number of times by reading the contents of REG 30 via input port 20 and data bus 21 using input port read signal 22. Next, the CPU accesses output point 10 and clock 11.
When a pulse occurs, FF40, 50.60 and REG
30 holds new information that holds the next state of the previous state.

Note that the same operation occurs when other events a and n occur.

〔Effect of the invention〕

As explained above, the present invention is capable of determining whether a certain event has occurred after collecting information once and before collecting information the next time. The same information can be collected from the register any number of times via It has the effect of increasing the

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information collection method according to the present invention, and FIG. 2 is a block diagram showing an embodiment of an information collection method according to the prior art. 10...Output port, 11...Clock, 12...
・Address bus, 13... Output port ride signal, 2
゜...Input port, 21...Data bus, 22...
・Input port read signal, 30...Register (REG)
)40.50,60,70,80.90...Flip-flop (FF)-41,71...Event a signal, 51
．． 81...Event signal, 61.91...Event n signal.

Claims (1)

[Claims] A holding circuit that holds a signal indicating that a certain event has occurred according to a clock, an output port that generates one pulse of the clock that determines the timing of holding when accessed by the CPU, and a signal held in the holding circuit. The holding circuit holds the signal in a flip-flop when an event occurs, and when the CPU accesses the output port and a clock pulse comes, this held signal is A signal is sent from the flip-flop to a register, the CPU accesses the output port and holds the signal in the register until the next clock pulse comes, and the CPU transmits the signal to the register via the input port. An information collection method characterized by collecting information from.