JPH02236896A - Memory circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Industrial applications The present invention relates to memory circuits.

2. Description of the Related Art When configuring a system using a conventionally used static RAM circuit, a circuit configuration as shown in FIG. 4 is generally used to latch the output of the RAM. FIG. 5 shows a timing diagram of this circuit.

The numbers in FIG. 5 are the same as in FIG.

In FIG. 4, 401 and 402 are data lines, which are complementary to each other. 401 is a positive logic data line;
02 is a negative logic data line, 403 is a sense amplifier, 40
4 is a flip-flop circuit, 405 is a memory cell, 40
B is a precharge circuit, 407 is a word line, 408 is an address decoder, 409 is a precharge signal, 4lO is the output of the sense amplifier 403, 4! l is clock, 412
is the output data.

By the precharge circuit 40G, the data lines 401, 4
02 are both precharged to a high state during the precharge period. When the precharging is completed and the word line 407 is selected by the address decoder 408, the contents of the memory cell 405 are read out. At this time, when the content of the memory cell 405 is "0", the positive logic data line 401 becomes low, and the negative logic data line 402 becomes high, so that the sense amplifier 403 senses that the content is "0". The output 41G of the sense amplifier 4G3 is input to the flip-flop circuit 404. And clock 411
By latching the data input to the flip-flop circuit 404 at the rising edge of
get.

Problems to be Solved by the Invention However, in conventional memory circuits, when the duty of the clock for latching changes, or when the input timing of the RAM address shifts and the delay time until data is read becomes large, There was a problem that the output data could not be latched correctly.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a memory circuit that can always accurately latch desired data.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention precharges a complementary data line and uses a clock generated using a change in the potential of the complementary data line caused by data reading. This device has a circuit that latches signals from complementary data lines.

Effect of the Invention The present invention provides a memory circuit which always accurately latches desired data by latching output data with a clock generated by detecting the state transition of the potential of the data line from which the output data is read. can be realized.

Embodiment FIG. 1 is a block diagram showing an embodiment of a memory circuit of the present invention. In FIG. 1, 101 and 102 are data lines, which are complementary to each other. 103 is a sense amplifier,
104 is a flip-flop circuit, 105 is a memory cell,
! 06 is a precharge circuit, 107 is a word line, 108
is an address decoder, l09 is a precharge signal, 11
0 is the data line potential transition detection circuit, 111 is the output of the sense amplifier 103, and ll2 is the data line potential transition detection circuit 11.
The output of 0 and lI3 are output data.

The data lines 101 and 10 are connected by the pre-charge circuit 10G.
2 are both the same during the precharge period, and are precharged to a constant potential. When the precharging is completed and the word line 107 is selected by the address decoder 108, the contents of the memory cell 105 are read out. At this time, the potential of either the data line 101 or the data line 102 becomes lower than the potential during the precharge period. A line potential transition detection circuit 110 detects the transition of this potential state.
The clock II2 is generated. Using this generated clock 112, the output 11 of the sense amplifier 103 is
1 is latched by the flip-flop circuit 104.

FIG. 2 is a circuit diagram showing one embodiment of the memory circuit of the present invention, and FIG. 3 is a timing diagram of this circuit, which will be explained in detail below. The numbers in Figure 3 are the same as in Figure 2.

In FIG. 2, 201 and 202 are data lines, which are complementary to each other. 201 is a positive logic data line;
02 is a negative logic data line, 203 is an OR circuit, 204
is a flip-flop circuit, 205 is a memory cell, 20B
is a precharge circuit, 207 is a word line, 208 is an address decoder, 209 is a precharge signal, 210,2
11 is an inverter circuit, 2l2 is an inverter circuit 210
, 213 is the output of the OR circuit 203, and 2I4 is the output data.

The data lines 201 and 20 are
2 are both precharged to the same high state during the precharge period, and the output of the OR circuit 203 becomes low. When precharging is completed and word line 207 is selected by address decoder 208, memory cell 2
The contents of 05 are read out. At this time, the memory cell 20
If the content of 5 is “0”, the positive logic data line 201
is low, the negative logic data line 202 is high, and the outputs of inverter circuits 210 and 211 are high and low, respectively. Then, the output of the OR circuit 203, that is, the clock 213 of the flip-flop circuit 204 changes from low to high. When the input data 212 of the flip-flop circuit 204 is compared with the clock 213 of the flip-flop circuit 204, the clock 213 is delayed by the gate delay time of the OR circuit 203. This means that the input data 212 of the flip-flop circuit 204
This indicates that the clock 2l3 is input to the flip-flop circuit after the
It can be seen that the value read from can always be accurately latched by the flip-flop circuit 204.

Note that the same effect as described above can be obtained even when the content of the memory cell is "'1". Further, even when the precharge level is not high, the same effect as described above can be obtained by setting the thresholds of the inverter circuits 209 and 210 lower than the precharge level.

Effects of the Invention As is clear from the above description, according to the present invention, desired data can be obtained by latching output data with a clock generated by detecting the state transition of the potential of the data line from which the output data is read. A memory circuit that always latches accurately can be realized. Furthermore, the circuit configuration can be easily realized, so
Its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a memory circuit in an embodiment of the present invention, FIG. 2 is a circuit diagram of a memory circuit in an embodiment of the present invention, FIG. 3 is a timing diagram of the circuit in FIG. 2, and FIG. 4 is a circuit diagram of a conventional memory circuit, and FIG. 5 is a timing diagram of the circuit of FIG. 101, 102, 201, 202...data line, 104.2041...flip-flop circuit, 105
, 205...Memory cell, 10[i, 20B...Precharge circuit,! IO...Data line potential transition detection circuit, 203...OR circuit, 210.211...
...Inverter circuit. Name of agent: Patent attorney Shigetaka Awano (1 name missing) 1 Figure 6 2 Figure 3 Figure 3 Grofuku

Claims (1)

[Claims] A memory comprising a circuit that precharges a complementary data line and latches a signal from the complementary data line using a clock generated using a change in potential of the complementary data line caused by reading data. circuit