JPH02237151A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a soft error by alpha rays and by a negative power-supply noise from an input terminal by a method wherein a gate electrode of a CMOS transistor is formed of an electrode of one conductivity type and a driver MOS constituting a memory cell is formed as a MOS transistor of one conductivity type. CONSTITUTION:In the figure, a bipolar transistor is formed in A, an nMOS transistor is formed in B, a pMOS transistor is formed in C and a memory cell is formed in D. Electrodes 10a extracted from a base region 9 of the bipolar transistor and gate electrodes 10b of the MOS transistor are formed of a p-type electrode layer; a driver MOS of a memory cell is formed as a pMOS; in addition, an n<+> type buried region is formed between an n-type region in which the memory cell has been formed and a p-type silicon substrate. Accordingly, the region where the memory cell has been formed is used as the n-type region; a junction is formed without forming a special region between the memory cell region and the substrate. Thereby, a soft error by alpha rays and a negative power-supply noise from an input terminal are cut off here; a malfunction of a memory is reduced; reliability can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device (Bi-CMOS memory) in which bipolar transistors and CMOS transistors are fabricated on one common silicon substrate.

[Conventional technology]

Conventional Bi-CMOS memory uses npn bipolar
Since transistors are used, the silicon substrate is limited to p-type, and since the memory cells are composed of nMOS transistors, they are p-type regions.

As a result, the region where the memory cell is formed and the substrate have the same conductivity type, and are susceptible to soft errors due to alpha rays and negative power supply noise, and an n-type region is provided between the two.

On the other hand, in order to increase the operating speed of the semiconductor memory device,
A structure is adopted in which an extraction electrode is provided from the base region of the bibolar transistor to reduce junction capacitance and base resistance. Furthermore, a structure in which the gate electrode of the MOS is of the p-type conductivity type and is shared with the bibolar base electrode (p-type) is also being considered. Related devices of this type include, for example, IEEE ELECTRON DEU, Electron Device Letters 8, 11 (1987), pp. 509-510.
ICELETTERS, VOL. EDL-8, N[l
11 (1987) PP509-51.1).

[Problem to be solved by the invention]

The former of the above conventional technologies improves reliability but does not take into account the simplification of the manufacturing process, and the latter does not take into account the miniaturization of memory cells, resulting in As technology advances, direct contact technology has been introduced for memory cells, but this technology has the problem of forming a junction at the contact area. An object of the present invention is to reduce soft errors caused by alpha rays or negative power supply noise from an input terminal in the semiconductor memory device, and to improve reliability of information in memory cells.

An object of the present invention is to provide the above-mentioned semiconductor memory device which is high speed and highly integrated.

[Means to solve the problem]

First, in order to reduce soft errors, the substrate and the area where the memory cells are formed must be separated by a junction, and if the above device is limited to a p-type substrate, the area where the memory cells are formed. would otherwise have to be an n-type area. Therefore, the driver MOS constituting the memory cell is a pMOS transistor, and the area where the memory cell is formed is an n-type area. Additionally, to reduce soft errors, an n-domain buried area of bipolar transistors is provided between the area where the memory cells are formed and the substrate.

Furthermore, in order to make the memory cell smaller in the above structure, it is necessary to eliminate the junction formed in the direct contact part, and the gate electrode of the MOS part is made of P-type conductivity type. At this time, it becomes the same conductivity type as the base lead electrode (p type) of the bipolar transistor.

[Effect]

In order to reduce soft errors, using pMOS as the driver MOS constituting the memory cell means separating the n-type area where the memory cell is formed from the p-type substrate by a junction, and the α Charges generated by the lines do not reach the MOS transistors forming the memory due to the junction, and malfunctions can be prevented. Furthermore, by providing an n-type area between the n-type area where the memory cell is formed and the p-type substrate (forming it at the same time as the n-type buried area of the bibolar transistor), it is possible to eliminate charges (especially holes) generated by alpha rays.
It works well to recombine the particles, and can further improve soft errors caused by alpha rays. Further, in order to reduce the size of the memory cell, by making the MOS gate electrode P-type conductivity type, formation of a junction at the direct contact portion can be prevented, and good contact characteristics can be obtained.

〔Example〕

Hereinafter, a typical embodiment of the present invention will be explained with reference to FIGS. 1 and 2, and a manufacturing process of the typical embodiment will be explained with reference to FIG. 3. Other embodiments are shown in FIGS. 4 and 5.

First, FIG. 1 shows that according to the present invention, on one silicon substrate,
The cross-sectional structures of the fabricated bipolar transistor, CMOS transistor, and memory cell are shown. A is a bipolar transistor, B is an nMOS transistor,
A PMOS transistor is fabricated at C, and a memory cell is fabricated at D. The present invention is characterized in that the electrode 10a drawn out from the base region 9 of the bipolar transistor and the gate electrode 10b of the MOS transistor are made of p-type electrode layers, that the driver MOS of the memory cell is made of a PMOS, Furthermore, the n-type area where the memory cell is formed and the P
The point is that an n◆-shaped buried area is provided between the shaped silicon substrates. Also, the gate electrode of the MOS transistor is p
As a result, an n-type region 8 is formed directly under the gate oxide film of the nMOS transistor for threshold voltage adjustment, resulting in a buried channel type.

on the other hand. The pMOS transistor becomes a surface channel type.

Next, the configuration of the memory cell will be explained using FIG. 2. FIG. 2(a) shows an equivalent circuit, and FIG. 2(b) shows a planar structure corresponding to FIG. 2(a).

As shown in FIG. 1 and FIG. 2(b), the driver MOS Qot shown in FIG. , a gate electrode 10 made of p-type polycrystalline silicon.
b-1, both sides of this gate electrode are made up of p-shaped areas 11a which are source/drain regions. Figure 2 (a
) is the driver MOSQo2 shown in
Similar to DI, it consists of a gate electrode 10b-2 made of a gate oxide film 6yP-type polycrystalline silicon, and p-shaped regions 1]-a which are source/drain regions on both sides of the gate electrode. The driver MOS shown in Fig. 2(a)
The cross-connection of the gate electrodes of QDI and QD2 is
'bar MOSQot (7) gate voltage +! 10b-1 is connected to the surface of the p-shaped region 11a which is a part of the drain region of the driver MOS QD2, and the driver MOS QD
The gate electrode 10b-2 of oz is connected to the driver MOS
This is done by connecting to the surface of the p-decade region, which is part of the drain region of QD1. The transfer MOS QTI shown in FIG. 2(a) has a gate oxide film 6, a word line W as shown in FIGS. 1 and 2(b),
It is composed of a gate electrode 10b-3 made of P-shaped polycrystalline silicon formed integrally with L, and a P-shaped region 11a which is a source/drain region. The transfer MOS QT2 shown in FIG. 2(a) is also a transfer MOS Q.
Same as TI. A p-shaped area that is part of the drain region of the transfer MOS is connected to the gate electrode of the driver MOS, and a p-shaped area that is part of the source region is connected to the data line DL. The resistance elements Rl and R2 shown in FIG. 2(a) are connected to the gate electrodes 10b-1 and 10b.
It is formed on the glabellar insulating layer covering -2 so as to overlap with the gate electrode. These resistance elements Rl and R2 are made of polycrystalline silicon 13 and are configured to have a resistance value of about 10 to 100 GΩ.

One end of each of the resistance elements Rl and R2 is connected to zero potential through the same layer of low-resistance polycrystalline silicon, unlike the conventional case where the transistor in the memory cell is nMOS.

Since the area where memory cells are formed is an n-type area,
Since a junction is formed without creating a special area between the memory cell area and the substrate, soft errors caused by alpha rays entering the substrate and negative power supply noise from the input terminal are cut here, reducing memory malfunctions. and reliability can be improved. Furthermore, since the memory driver MOS has a P-type gate, direct contact is possible and the memory cell can be made smaller.

FIGS. 3(a) to 3(d) are cross-sectional views at each manufacturing step of this embodiment. In Figure 2 (a), first, the specific resistance is 10Ω.
・Provide silicon oxide and silicon nitride films with a thickness of 10 to 100 nm on a p-type silicon substrate of about The silicon oxide film is etched one after another. Antimony is then diffused into the area by thermal diffusion.

Thereafter, the remaining silicon nitride film and silicon oxide film are etched one after another, and single crystal silicon having a thickness of 500 to 3000 nm is epitaxially grown on the substrate to form an n-dos shaped buried region 2. Furthermore, a silicon oxide film and a silicon nitride film with a thickness of 10 to 600 nm are provided on the single crystal silicon, and using photoresist technology, the silicon nitride film is dry etched in the areas where bipolar transistors and PMOS transistors are to be fabricated. Phosphorus, which is an n-type impurity, is ion-implanted using resist and silicon nitride as masks. After removing the remaining resist, an oxide film with a thickness of 50 to 500 nm is formed by a method of selectively forming an oxide film, and boron, which is a P-type impurity, is ion-implanted using this as a mask. Here, heat treatment was performed at 1000°C for 1 hour to reduce the impurity concentration to 1015 to 1017 an
-', an n-type region 3 and a p-type region 4 having a depth of about 1 to 5 μm are formed, and the oxide film previously used as a mask for ion implantation is etched.

In FIG. 3(b), in order to electrically isolate each element on the substrate, the selective oxidation method described above is used to
A field oxide film (l! silicon dioxide) 5 of m is formed between each element. Although not shown in the figure, impurity concentration IQ1 is added directly under the field oxide film to ensure isolation.
1I1 to 10l8an''''2 p-type zones may be formed. Subsequently, a gate oxide film 6 with a thickness of 5 to 50 nm is formed in the portions that will become the active regions of the bipolar transistor and MOS transistor. Next, phosphorus, which is an n-type impurity, is ion-implanted into the area that will become the collector of the bibolar transistor using photoresist technology, and heat treatment is performed at 1000°C for 30 minutes to connect it to the n-type buried area. Then, an area 7 with an impurity concentration of 1017 to 2020 -8 is formed. Next, for threshold voltage adjustment, MOS}-
Arsenic, which is an n-type impurity, is ion-implanted into the region where the transistor is to be formed using photoresist technology. As a result, an n-type area 8 is formed in the region where the nMOS transistor is formed, and the nMOS transistor becomes a buried channel type. Furthermore, using photoresist technology, boron, which is a P-type impurity, was ion-implanted into the base region of the region where the piebora transistor was to be formed.
After heat treatment for about 30 minutes, the impurity concentration was reduced to 10tI1-1.
A p-type area 9 is formed which will become the base region of 017C111''''3.

In FIG. 3(c), first a polycrystalline silicon pancreas is deposited, which will become the base lead electrode of the bipolar transistor and the gate electrode of the MoS transistor. At this time, the gate oxide film 6 in the base region and the silicon substrate of the memory cell where the electrodes of both are connected (direct contact portion) is removed. After the polycrystalline silicon film is deposited, it is a P-type impurity. Boron ions are implanted at an areal density of about 1016 .mu.-2, and heat treatment is performed at 950.degree. C. for about 10 to 30 minutes. Next, using photoresist technology and existing etching technology, both electrodes are processed into a predetermined shape by one dry etching process to obtain P-type polycrystalline silicon 10. Here, the p-type polycrystalline silicon may be a double layer of p-type polycrystalline silicon and metal silicide. Further, using photoresist technology, p-shaped areas 11a. An n+ type area 12 is formed. The p-decade region 1lb shows that boron, which is an impurity, seeps out from the polycrystalline silicon.

In FIG. 3(d), in order to form a high resistance in the memory cell section, an interlayer insulating film is first buried, and then a dry/<MOS
A high-resistance connection is opened using photoresist technology and existing etching technology, and a second layer of polycrystalline silicon is deposited. Here, boron, which is a p-type impurity, is ion-implanted into polycrystalline silicon and processed into a predetermined shape to obtain polycrystalline silicon high resistance 13. Further, this polycrystalline silicon may be used to form a shallow emitter in a bipolar transistor. Next, in order to provide a metal film, an interlayer insulating film 14 made of silicon-based oxide is formed. In this example, in order to form an emitter, holes are first opened only in the region where the emitter will be formed, and arsenic, which is an n-type impurity, is formed. ion implantation, 900
℃, for about 10 to 30 minutes to reduce the impurity concentration IQ1.
Obtain an n-shaped area 15 (emitter region) of 7 to 20■-3. Finally, using a conventional technique, a connection hole is made in a portion of each element to be connected to the metal film, and after depositing a metal such as aluminum, the metal film 16 is processed into a predetermined shape. Typical embodiments are realized through the above manufacturing process.

The embodiment shown in FIG. 4 is a typical embodiment in which the n-type buried layer in the area where the memory cell is formed is removed, and the distance between the bipolar transistor and the memory cell is shortened. It has the effect of In the embodiment shown in FIG. 5, a p-shaped region is formed between the n÷-shaped buried region of the typical embodiment, and a p-shaped region is formed between the bipolar transistors and between the bipolar transistor and the memory cell. It has the effect of closing the distance.

〔Effect of the invention〕

According to the present invention, conventionally, the gate @ pole of CMOS is n-type,
Since the base extraction electrode of Bibolar was p-type, it was difficult to process the electrodes at the same time, but by making the gate electrode P-type conductivity, the electrodes could be formed in the same manufacturing process. The manufacturing process can be made easier than before (reducing the number of steps)
effective.

Furthermore, PM of n-type gate! By changing the OS transistor to a p-type gate PMOS transistor, the conduction mechanism of the pMOS becomes a surface channel type, which also has the effect of improving the short channel characteristics of the pMOS}-transistor.

[Brief explanation of drawings]

Figure 1 is a completed cross-sectional structural diagram of a typical embodiment of the present invention, Figures 2 (a) and (b) are a plan view and circuit diagram, and Figure 3 (a).
) to (d) are cross-sectional configuration diagrams of important stages of the manufacturing process in FIG. 1, and FIGS. 4 and 5 are completed cross-sectional configuration diagrams of other embodiments. DESCRIPTION OF SYMBOLS 1...p-type silicon substrate, 5...field oxide film, 10...p-decade polycrystalline silicon M (bipolar transistor electrode and MOS gate electrode), 13...P
Polycrystalline silicon high resistance, 14...Interlayer insulating film, 16
...metal film, A... bibolar transistor area,
B...n M O S transistor area, C...
pMOst #Zril (a no 2nd ω(b)

Claims (1)

[Claims] 1. In a semiconductor memory device in which a bipolar transistor and a CMOS transistor are fabricated on a semiconductor substrate of one conductivity type, the gate electrode of the CMOS transistor is formed with an electrode layer of one conductivity type to constitute a memory cell. A semiconductor memory device characterized in that a driver MOS is a MOS transistor of one conductivity type. 2. In the semiconductor memory device according to claim 1, a region of the other conductivity type with a high impurity concentration is provided between the region of the other conductivity type in which the memory cell is formed and the substrate of the one conductivity type. A semiconductor memory device characterized in that: 3. A semiconductor memory device according to claim 1, wherein the base electrode drawn out from the base region of the bipolar transistor is of one conductivity type.