JPH0223720A - semiconductor circuit - Google Patents

Abstract

PURPOSE:To automatically compensate dispersion on a manufacture condition so as to eliminate the operation fluctuation of a circuit by changing the resistant value of a bias supply resistant element in correspondence with the threshold of current power FET. CONSTITUTION:When a signal input into a terminal In is changed from 'L' to 'H', the discharge of a charge in a load circuit depends on the threshold of power FET4, and depends on a signal impressed on the gate of FET4 through a circuit consisting of a capacity element 30 and the bias supply resistant element 40. When the threshold of FET 4 is small, the resistant value of the element 40 becomes large, and the quantity of the signals given to the gate of FET4 becomes large. When the threshold of FET4 is large, the resistant value of the element 40 becomes small. As a result, the driving force of FET4 is compensated by a CR time constant, and the dispersion of a characteristic due to that of the manufacture condition is cancelled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor circuit, and is used, for example, as a logic gate in a digital integrated circuit using a Schottky gate field effect transistor.

[Conventional technology]

Traditionally, BFL (Burfered PET
Logic gates called Logic circuits are known. As shown in FIG. 3, this includes a switch stage 10 and a buffer stage 20. A signal is input to the switch stage 10 from a signal input terminal IN, and the buffer stage 20 receives a signal from a signal input terminal IN.
A signal is output from the signal output terminal OUT. Here, the switch stage 10 includes a switching FETI whose gate is connected to the signal input terminal IN, and a load FET 2 whose source and gate are connected to the drain of this switching FETI. A source follower FET3 whose gate receives the output of the switching FETI, a level shift diode D whose anode is connected to the source of this source follower FET3, and a current source whose drain is connected to the cathode of this level shift diode D. FET4.

In the circuit shown in FIG. 3, when the signal input terminal IN changes from H (high level) to low level, the gate of the source follower FET3 changes from L to H, and conversely, the signal input terminal IN changes from L to H. Source follower FET
The gate of No. 3 changes from H to L, and therefore the signal output terminal O
A signal output obtained by inverting the signal input to the signal input terminal IN is obtained at the UT. At this time, signal output terminal O
Various load circuits (not shown) are connected to the UT, and therefore it is necessary to quickly discharge the charges accumulated in these load circuits.

[Problem to be solved by the invention]

In recent years, as digital integrated circuits have become more highly integrated and larger in scale, there has been a demand for logic gates that can drive long wiring loads. As such, attempts have been made to, for example, generate a signal that is in phase with the input signal to the switching FET, that is, a signal that is an inversion of the output signal, and input this signal to the gate of the current source FET. .

According to this, the current source FET is a source follower FET.
Since the push-pull operation is also performed, the load driving ability can be improved.

However, in this configuration, large variations occur in the driving ability due to variations in characteristics (particularly variations in vth) of elements such as current source FETs. For this reason, there arises a drawback that it becomes difficult to obtain a semiconductor circuit with a high yield that achieves a predetermined load driving capability while simultaneously realizing low power consumption and high-speed operation.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor circuit that can realize sufficiently high load driving capability with low power consumption and can increase manufacturing yield.

[Means to solve the problem]

The semiconductor circuit according to the present invention includes a switch stage, a buffer stage,
The switch stage includes a capacitive element and a bias supply resistance element, and the switch stage includes a switching FET whose gate is connected to a signal input terminal, and a load connected in series with the switching FET.

Further, the buffer stage includes a source follower FET whose gate is connected to the output terminal of the switch stage, and a current source FET connected in series with the source follower FET. A signal that is the inversion of the output is supplied to the gate of the current source FET via the capacitive element, and the bias supply resistor element is connected to the current source FET gate, which activates the current source FET. It is characterized by being formed under the same conditions as the layer.

[Effect]

According to the configuration of the present invention, when the vth of the current source FET is shallow, the resistance value of the bias supply resistance element becomes high, and when the vth of the current source FET is deep, the resistance value of the bias supply resistance element becomes low. Therefore, it is possible to automatically compensate for variations in manufacturing conditions and eliminate variations in circuit operation.

〔Example〕

Hereinafter, the present invention will be described in detail based on FIG. 1 of the accompanying drawings. In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.

FIG. 1 is a circuit diagram of a semiconductor circuit according to a first embodiment.

The difference between this and the conventional circuit (BFL circuit) shown in FIG. 3 is that the gate and source of current source FET 4 are not short-circuited, and the current source FET 4 and switching FET
The gate of I is connected via a capacitive element 30,
A bias supply resistance element 4 is connected to the gate of the power supply FET 4.
0 is connected. Furthermore, a characteristic feature of the present invention is that the bias supply resistance element 40 is formed on a semiconductor substrate (not shown) under the same conditions as the active layer formation of the power supply FET 4, that is, through the same ion implantation process, etc.
It consists of a semiconductor resistor formed on top.

Next, the operation of the above embodiment will be explained.

When the signal input to the signal input terminal IN is L, the gate voltage of the source follower FET3 becomes H, so the source follower FET3 is turned on and the current flowing through the level shift diode D is supplied to the load circuit from the signal output terminal OUT. Ru. At this time, the gate voltage of the current source FET 4 temporarily becomes low following the level change of the signal input terminal IN, and therefore the current flowing through the current source FET 4 is small. Therefore, current consumption can be kept low.

When the signal input to the signal input terminal IN changes from L to H, the gate voltage of source follower FET3 changes from H to L,
Therefore, the source follower FET3 changes from on to off.

At this time, the gate voltage of the current source FET 4 follows the level change of the signal input terminal IN and becomes temporarily high. Therefore, the current flowing through the current source FET 4 increases, so that the load connected to the signal output terminal OUT The charge in the circuit (not shown) is quickly discharged. For this reason, especially when the output changes from H to L.
It is possible to increase the load driving capacity when changing to

Next, when the signal input to the signal input terminal IN returns from H to L, the gate voltage of the source follower FET 3 returns to H as described above, and the gate voltage of the current source FET 4 temporarily decreases. .

Therefore, the source follower FET 3 and the current source FET 4 function close to push-pull operation.

In the above circuit operation, especially the signal input terminal IN
The discharge of the charge in the load circuit when the signal input changes from L to H depends firstly on the vth of the power supply FET 4, and secondly depends on the vth of the power supply FET 4, and secondly through the circuit consisting of the capacitive element 30 and the bias supply resistance element 40. It depends on the signal applied to the gate of the power supply FET 4. Therefore, first of all, due to the manufacturing conditions (conditions for ion implantation, etc.) when forming the active layer of the power supply FET 4,
Considering the case where the vth of the power supply FET 4 is shallow, in this case the load driving force of the power supply FET 4 is small. However, since the bias supply resistance element 40 formed under the same conditions as the active layer of the power supply FET 4 has a large resistance value, the CR time constant due to the capacitive element 30 and the bias supply resistance element 40 becomes large. The amount of signal applied to the gate of the FET 4 also increases, and the push-pull effect increases. As a result, the power supply FET
The low driving force of FET 4 itself is offset by the large time constant of capacitive element 30 and bias supply resistance element 40, and the load driving force of the actual circuit becomes larger than that of power supply FET 4 itself.

Next, when the vth of the power supply FET 4 is deep due to the manufacturing conditions when forming the active layer of the power supply FET 4, the resistance value of the bias supply resistance element 40 becomes low due to the same manufacturing conditions.

Therefore, although the load driving force of the power supply FET 4 itself becomes high, the above-mentioned CR time constant becomes small, and therefore the push-pull effect becomes small. As a result, the high driving force of the power supply FET 4 itself is compensated for by the small CR time constant, and variations in characteristics due to variations in manufacturing conditions are offset. Therefore, a logic gate circuit that can reduce current consumption while maintaining sufficient load driving capability can be realized with high yield.

FIG. 2 is a circuit diagram of a semiconductor circuit to which another embodiment of the present invention is applied.

This circuit differs from the BFL configuration shown in FIG.
L (Source Coupled PET Log
ic). FET II forming the switch stage
, 12 gates are connected to the input signal (IN) and the reference voltage (RE
F) is given, and a current source I is connected to this differential configuration circuit. One buffer stage consists of FETs 31.41 and level shift diode D, and the other buffer stage consists of FETs 32, 42 and level shift diode D.

Here, the capacitive elements C are current source FET41,
42 and the drains of switch FETs 11 and 12, this is to supply a signal inverted from the output (OUT) to the gates of FETs 41 and 42 via capacitive element C. . What is important in this embodiment is that the bias supply resistance element R is formed under the same conditions as the active layers of the current source FETs 41 and 42. Thereby, the same effects as in the first embodiment described above can be achieved.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, the number of level shift diodes is not limited to one, and may be provided in multiple stages. Alternatively, it may not be provided at all. When the level shift diode is omitted, the circuit of FIG. 1 can be used in a circuit such as an output buffer of an IC where the logic level of the output may be higher than that of the input.

Alternatively, by setting the vth of the FETs forming the circuit to different conditions, it is possible to make the logic level of the output the same as that of the input. Specifically, in the circuit of FIG. 1, FETs 2 and 4 are depletion type, and FETI,
3 may be an enhancement type.

〔Effect of the invention〕

As explained in detail above, in the present invention, the current source FET
When vth of the current source FET is shallow, the resistance value of the bias supply resistance element becomes high, and when vth of the current source FET is deep, the resistance value of the bias supply resistance element becomes low. Therefore, it is possible to automatically compensate for variations in manufacturing conditions and eliminate fluctuations in circuit operation, making it possible to achieve sufficiently high load driving capability with low power consumption, and also to increase manufacturing yields. A circuit is obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a semiconductor circuit according to another embodiment;
The figure is a circuit diagram of a conventional BFL circuit. 1... Switching FET, 2... Load FET
. 3... Source follower FET, 4... FE for electric ui
T. D... Level shift diode, 10... Switch stage, 20... Buffer stage, 30... Capacitive element, 4
0...Bias supply resistance element, IN...Signal input terminal, OUT...Signal output terminal. Patent applicant: Sumitomo Electric Industries, Ltd. Patent attorney Yoshiki Hase Conventional BFL circuit diagram 3

Claims (1)

[Claims] 1. A switch stage including a switching FET whose gate is connected to a signal input terminal and a load connected in series to the switching FET, and whose gate is connected to the output terminal of the switch stage. A semiconductor circuit comprising a buffer stage including a source follower FET and a current source FET connected in series with the source follower FET. and a bias supply resistance element formed under the same conditions as the active layer of the current source FET so as to supply a predetermined bias to the gate of the current source FET. Characteristic semiconductor circuit. 2. The semiconductor circuit according to claim 1, wherein the source follower FET and the current source FET are connected via at least one level shift diode.