JPH02238558A - Boot system for parallel computer - Google Patents

Abstract

PURPOSE:To increase the number of processor elements by executing successively the boot programs received from a communication port via a CPU at the side of each processor element after a host computer detects that all processor elements has accesses to the communication port. CONSTITUTION:In a reset state an address decoder 4c decodes the address data received from a CPU 4a and has an access to a communication port 4b. A host computer 1 sends a boot program to each processor element PE 4 when the computer 1 detects that all processors PE 4 has accesses to the port 4b. Then each PE 4 carries out successively the boot programs received from the port 4b via the CPU 4a. Thus the computer 1 gives a program to each PE 4 in an initial program load IPL state. As a result, each PE requires no ROM storing an IPL program and the number of elements PE is increased.

Description

[Detailed Description of the Invention] [Summary] One host computer and a plurality of processor elements 1.
The purpose of the present invention is to provide a boot method for distributed memory parallel computers that are connected via a bus, so that each processor can take full advantage of the advantage of increasing the number of processor elements in a distributed memory parallel computer The element is equipped with a CPU, a communication port connected to the bus, and an address decoder that decodes the address output from the CPU when the processor element is reset and accesses the communication port, so that all processor elements communicate. When the host computer detects that the port has been accessed, the host computer sends a boot program to each processor element, and each processor element sequentially executes the Boolean program manually input from the communication port by the CPU. Configure it as follows.

[Industrial Field of Application] The present invention relates to a distributed memory parallel computer system in which one host computer and a plurality of processor elements are connected via a bus.

In recent years, there has been a demand for faster computer systems. A parallel 51 computer is used as one method for achieving higher speeds. Here, a parallel computer is a computational element (processor element) that executes a program.
A single computer is constructed by combining a plurality of Elements (hereinafter abbreviated as PE). Broadly speaking, there are two possible implementation methods for this type of parallel computer.

One is a shared memory type parallel computer in which a large memory is shared by multiple PEs, and the other is a distributed memory type parallel computer in which each PE has an independent memory. The latter distributed memory type parallel computer has the characteristic that it is possible to increase the number of PEs. However, one PE
If the amount of hardware increases, this feature cannot be utilized.

Therefore, it is necessary to keep the amount of hardware in the PE small. Additionally, as the number of PEOs increases, efficient boot methods are required.

[Prior Art] FIG. 7 is a block diagram of a conventional distributed memory parallel computer. One host 1/51 calculator 1 and multiple PEs
2 are connected via a bus 3.

FIG. 8 is a diagram showing an example (conventional) internal configuration of each PE.

As shown in the figure, the PE is composed of a communication port 2a connected to a bus 3, a RAM 2b, a CPU 2c, a ROM 2d, and an internal bus 2e connecting these. ROM2
A boot-up (IPL. initial program load) program is stored in d.

Boot-up (IPL) of the distributed memory type parallel computer configured in this way is performed by a program stored in the ROM 2d prepared in the PE. FIG. 9 is a flowchart showing a conventional boot-up procedure.

First, the user initializes the host 1 and computer 1 (S1)
. After that, the host 1 and computer 1 start IPL (S2
). Next, the host nI computer initializes PE2 as one procedure of IPL (S3).

Each PE2 starts executing the IPL program stored in the ROM2d (S4). Next, host computer 1
transmits the OS etc. to PE2 via bus 3, and
E2 installs the OS, etc. on the host computer 1 during the IPL execution process.
from the bus 3 (S5). And each PE
2 ends IPL and starts operation, and host computer 1 ends IPL and starts operation (S6). Here, the operation refers to the original parallel processing operation.

[Problems to be Solved by the Invention] In the conventional system, a ROM in which a boot program is written is prepared for each PE, and boot-up (IPL) is performed using the program. However, this configuration requires a certain amount of hardware including the ROM and the like. Furthermore, it is necessary to prepare as many ROMs as there are PEs, which may lead to an increase in cost when manufacturing the system and a decrease in reliability during operation. Due to the above,
In the conventional system, it was not possible to take full advantage of the advantage of increasing the number of PEs.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a boot method for a parallel computer that can fully utilize the advantage of increasing the number of PEs in a distributed memory parallel computer. It is said that

[Means to solve the problem] First. The figure is a block diagram of the principle of the system of the present invention.

Components that are the same as those in FIG. 7 are designated by the same reference numerals.

In the figure, ] is a host 1/computer, 3 is a bus, and 4 is a plurality of PEs connected to the bus. Within each PEJ, C
PU4a, communication port 4b connected to bus 3, and P
The address decoder 4c decodes the address output from the CPU 4a at the time of resetting the E, and accesses the communication ports 1 and 4b, and a RAM 4d. Although the figure shows the internal configuration of one PE, the same applies to other PEs.

[Function] At the time of reset, the address decoder 4c decodes the address data output from the cPU 4a and opens the communication port 1.
・Enable access to 4b.

Then, when the host computer 1 detects that all PEs 4 have accessed the communication port 4b, the host 1/computer 1. The Boo 1 program is sent to each PE 4 from the CPU 4a, and on each PE 4 side, the Boo 1 program input from the communication boards 1 and 4b is sequentially executed by the CPU 4a. With this configuration, the program during IPL is provided to each PE4 from the host 1 and computer 1, so a ROM storing the IPL program is not required in each PE4. Therefore, according to the tree invention method, the advantage of being able to increase the number of PEOs in a distributed memory parallel computer can be fully utilized.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail in comparison with conventional examples with reference to the drawings.

The present invention provides a system that does not require a ROM by devising a method for decoding the address space visible from the CPU of the PE. FIG. 2 is a diagram showing an address space, in which (a) shows a conventional address space, and (b) shows an atrus space according to the present invention. Here, we make the following assumptions. First, when the PE CPU is initialized (reset) as a post I/computer, atlus ooo
The instruction is taken from o (# indicates hexadecimal) and execution begins. Data from the bus is port 1 (address FOO
O. ) by reading. All addresses are in hexadecimal, and the values shown in the figure are examples.

The conventional address space has an address o as shown in (a).
ooo. ~2000# was allocated to the ROM, and the IPL program was stored here. After (7) 2
0 0 0 # - F O O O #matei;i
A RAM area and a PORT (port 1) area were appropriately allocated. Then, when PE is initialized, P
In E (7) CPULi7 dollar l/s0 0 0 0 #
The IPL stored in the ROM placed between 2000m from
(created by a computer) from port 1 and RA
Write to M.

On the other hand, in the case of the present invention, the addresses 0000# to 2000m are used as the addresses of voice I., as shown in (mouth). Therefore, when the PE is initialized, the CP in the PE
When U outputs an address as oooo#, the address decoder shown in FIG. 1 decodes this address and converts it to baud 1, a1, address, and accesses the communication port.

During this time, the IPL blockram is transferred from the host computer to each PC.
E, and each PE sends the program to the CPU via communication board 1. It is to execute II)L. Therefore, according to the present invention, a ROM storing an IPL program is not required.

Next, the data that the host/computer sends to the PE and the PE's CP
The relationship between the instructions executed by U will be explained in more detail. Here, the instructions executed by the CPU of the PE are defined as follows.

STADDR. Write the register value to address (ADDR) LD ADDR , address (ADDR)
In addition, the OS data string that the host computer sends to the PE is read into the register.
Assuming that OSZ is written as O, OSI, ... OSZ (assuming that the number of final data 1 data is 100#),
Data and PE sent from the host computer to the PE using the conventional method
The instruction sequence executed by the CPU is as shown in FIG. The period from time t to t2 is a sequence in which the host computer transmits the OS to each PE.

Figure 4 shows the data sent to the host computer or PE and the PE's CP.
It is a figure which shows the example of an instruction (this invention) which U executes. In the conventional example, only OS instructions are given from the host 1/computer as shown in FIG. 3, but in the case of the present invention shown in FIG. 4, the host computer receives not only OS instructions but also LD.
It is sending commands FOOOs and ST 20DOm.

In the conventional system, these instructions are given from the built-in ROM. On the PE side, when this LD command is received from the communication port, it is executed as a CPU command. In other words, on the PE side, the address 000 output from the CPU
All communication port addresses from 01 to 2000m are FOOO
Convert the data input from the communication port to # and send it to the CPU.
The command is taken in as an instruction to be executed and the execution proceeds.

In FIG. 4, the range from time t1 to t2 is the sequence in which the OS is transmitted from the host computer to each PE. As mentioned above, the instructions executed by the PE CPU are also executed by the host 1.
It is sent from the computer to the PE. In other words, the IPL, which was conventionally stored in the ROM, is performed using an instruction sent from the host computer. Therefore, it is no longer necessary to prepare a ROM in each PE. This was made possible due to the above-mentioned address decoding technique. I will explain further. P
After initialization, the CPU in E is at address oooo. Start execution from.

Then, the instruction is read from address oooo and executed, and then the okara instruction from address 0001 is read and executed. In this way, the process is executed while updating the addresses one by one. Conventionally, IPL was executed by placing a ROM in which IPL was written in the address space starting from address 0000. In the present invention, a communication port is allocated to this space, and after the CPU is initialized, instructions are sent to address oooo. If an attempt is made to read from the host computer, the data of the communication port, that is, the command sent from the host computer via the bus, will be read.

FIG. 5 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals.

Although only one PE is shown in the figure, a plurality of PEs are actually connected to the bus 3.

The host computer 1 includes a CPUia, a memory 1b, and a bus 3.
The PE 4 is configured with an interface section]C that controls connection with the PE4 via the interface section C. This interface section 1c
In addition to the bus 3, a control line 5 is also connected to the . This control line 5 is also connected to each PE4. P.E.
4, 4e is an interface unit that controls connection with the host computer 1 via the bus 3, and 4f is a P E J
There is an internal bus inside. Communication port 4b shown in Figure 1
is included in the interface section 4e. The operation of the system configured as described above will be explained as follows.

FIG. 6 is a diagram showing a boot sequence according to the present invention. The operation of the system shown in FIG. 5 will be explained below along with this sequence diagram. First, a reset signal is output from the host 1/computer 1 to the PE via the interface section C (■). On the other hand, on the PE4 side, upon receiving the reset signal sent via the interface section 4e, the internal state is reset and initialized ((1)). When reset, the CPU 4a fetches and executes instructions from address 0000#. Therefore,
The CPU 4a has the address oooo. is output as address data. This address data is sent to address decoder 4.
c is converted into a signal for accessing the communication port in the interface section 4e. As a result, the communication port is accessed ((2)). However, control line 5
Since the ACK signal (acknowledgment signal) has not yet become valid, the device remains in a hold state ((3)).

On the other hand, on the host computer side, the CPU 1a monitors access by all PEs 4 to the communication port 4b via the interface unit 1c.

Then, wait until all PEs access the communication ports and output the PE's first command to the communication port 4b (■)
. At the same time, the ACK signal on the control line 5 is enabled (■).

On the PE side, the ACK signal was held until it became valid, but when the ACK signal became valid, the CPU4
a reads and executes the first instruction ((4)). Next, C
When the PU 4a outputs the address signal 0 0 0 1-s for fetching the second instruction, this data is again converted by the address encoder 4c into a signal for accessing the communication ports 1 and 4b, and the address signal 0 0 1-s is used to access the communication port 4c. ((5)).

At this time, the ACK signal is in an invalid state, so the AC
It is held until the K signal becomes valid ((6)).

The host computer side waits for all PEs to access the communication port 4b, and then sends the PE's next command to the communication port 4b.
Output to (■). At the same time, the ACK signal on the control line 5 is enabled (■).

On the PE side, the second command is read and executed via the communication port 4b ((7)). In this way, on the PE side, C
The instruction (instruction address) fetched by PU4a is IFF
Repeat (5), (6), and (7) until F# is not exceeded ((8)). On the other hand, on the PE side, ■ and ■ are repeated until the boot sequence is completed (■). When the OS is sent from the host computer, the host computer only needs to send the OS data in accordance with the instructions to be executed by the PE, as shown in FIG.

[Effects of the Invention] As described above in detail, according to the present invention, after the PE is reset, the CPU in the PE decodes the address output for instruction fetch and converts it into a signal for accessing the communication port 1. The ROM in the PE can be made unnecessary by converting the data and receiving the command for IPL from the POS 1 autopsy machine via the communication port. Therefore, according to the present invention, it is possible to fully utilize the advantage of being able to increase the number of PEs in a distributed memory parallel computer.

[Brief explanation of drawings]

Figure 1 is a principle block diagram of the method of the present invention, Figure 2 is a diagram showing the address space, and Figure 3 is a diagram showing the data sent by the host computer to the PE and the CP of the PE.
FIG. 4 is a diagram showing an example of an instruction executed by U (conventional), FIG. 4 is a diagram showing data sent from a host computer to a PE, and an example of an instruction (present invention) executed by the PE's CPU, and FIG. 5 is an example of an implementation of the present invention. FIG. 6 is a configuration block diagram showing an example of the boot sequence according to the present invention. FIG. 7 is a configuration block diagram of a conventional distributed parallel computer. FIG. 8 is an example of the internal configuration of each PE (conventional). The figure shown in FIG. 9 is a flowchart showing the conventional boo1-up procedure. In FIG. 1, 1 is a host computer, 3 is a bus, 4 is a PE, 4a is a CPU, 4b is a communication port, 4c is an address decoder, and 4d is a RAM. ] 7 Conventional ■Distributed memory type parallel computer■Configuration diagram No. 7
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Claims (1)

[Claims] In a distributed memory parallel computer in which one host computer (1) and a plurality of processor elements (4) are connected via a bus (3), in each processor element (4) , a CPU (4a), a communication port (4b) connected to the bus (3), and an address decoder that decodes the address output from the CPU (4a) when the processor element is reset and accesses the communication port (4b). (4c), and all processor elements (4) have communication ports (4b
) is detected on the host computer (1) side, the host computer (1) sends a boot program to each processor element (4), and each processor element (4) side sends a boot program to the communication port (4).
The boot program input from b) is sent to the CPU (4a)
A boot method for a parallel computer, characterized in that it is configured to be executed sequentially.