JPH0223892B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address control method for a computer system, and more particularly to a method for automatically updating an address register independent of a CPU each time the CPU accesses the address register.

Conventionally, the addressable address space of a CPU was fixed by its hardware, so if the address space was insufficient, address calculation means and address setting means were added and extended memory was added, effectively increasing the address space. Although the address space was expanded in a similar manner, the disadvantage was that the processing time was long.

SUMMARY OF THE INVENTION An object of the present invention is to provide a system that can eliminate the above-mentioned drawbacks and perform efficient address translation.

This purpose is a central processing unit (hereinafter referred to as CPU)
In a computer system in which addresses of other devices are controlled by the address register of the
This is achieved by an address control method characterized by providing an address register independent of the CPU and updating the contents of the address register each time the address register is accessed by the computer system.

The present invention will be explained in detail below using the drawings.

FIG. 1 is an overall block diagram showing one embodiment of the present invention. In the figure, 1 is the CPU section, 2 is the
ROM part, 3 is RAM part, 4 is IO part, 5 is expansion part,
6 is a control bus, 7 is an address bus, and 8 is a data bus.

FIG. 2 is a block diagram showing the detailed operation of the expansion section 5 according to an embodiment of the present invention.

In the figure, 10 is an address control section, 11 is a data control section, 12 is a ROM table section (or expansion data memory), 13 is a connection line with the system control bus, 14 is a system address bus, and 15 is a connection line with the system data bus. A connection line 16 is a signal line for notifying the address control section that the extension section has been accessed, 17 is an extension address line, and 18 is an extension data line.

FIG. 3 is a block diagram showing details of an address control section and a data control section showing one embodiment of the present invention.

In the figure, 19 is a clock, 20 is a write signal, 21 is an address recorder output line, 22 is an address recorder output line, 50 is a gate A, 51 is a gate B, 52 is a gate C, and 53 is a gate D (AND
circuit), 54 is gate E, 55 is gate F, 56
is OR gate G, 58 is 3-state buffer A,
59 is 3-state buffer B, 60 is address record A, 61 is multiplexer, 62 is FFA
(address register A), 63 is FFB (address register B), 64 is an adder, and 65 is address recorder B.

FIG. 4 is a block diagram showing a modification of one embodiment of the present invention.

In the figure, 30 is for the interface.
RAM, 31 is handshake line, 70 is
CPUA, 72 is CPUB.

Now, when the fixed address space is insufficient, an expansion memory is added to substantially expand the address space. For example, the extension unit 5 is used for storing sequential data such as when accessing an MT, and for reading and writing fixed data such as a record conversion table.

Also, to explain the operation of the CPU 1 reading N words of data from the ROM table 12 as an example, the CPU 1 first uses the system address 14 to specify the read start address of the ROM table 12.
Read the address of the address register A62 to the system data bus 15 from the ROM table 12, set the start address, and write it to the address control unit 10. Next, write the address of the address register A62 to the system address bus 14 to specify the addition value of the address register A62. The added value is set in the added value register address and the system data bus and written to the address control unit 10.

Furthermore, when the data control section address is set on the system address bus 14 and the data control section 11 is read in order to read the extended data memory for the first time, the address specified by the address register A62 is set on the system data bus 15. The data stored in is read out. When the read is completed, a value obtained by adding the addition value to the read start address is output to the extended address line 17 in preparation for the next access. Subsequently, by executing the read operation of the ROM table 12 (N-1) times, N words of data are read.

Next, the address control section and data control section will be explained in detail. The address control unit 10 includes an address register A62 that holds an extended address, and an address register B63 and FFA62 that hold values to be added to or subtracted from the address register A62.
It is composed of an adder 64 and the like that adds (or subtracts) the contents of the FFB 63 to calculate a new value to be set in the address register.

The data control unit 11 includes a bidirectional driver/
Receiver (58, 59) and access notification signal 16
It is composed of an AND circuit 53 and the like that generates.

Further, the function of setting the access start address in the address register A62 is performed as follows.

The address of the extended address register is set on the system address bus 14, the address decoder A60 operates, its output line 21 is activated, and the multiplexer 61 inputs the contents of the system data bus 15 to the address register A62.

On the other hand, the write signal 20 and clock 19
The ANDed signal is gate A50, gate B
51 and is applied as a clock input to address register A62 through gate G56.

, address register A62
An access start address is set in , and output to the extended address line 17 .

Note that the procedure for setting the addition value in the address register B63 is performed in the same manner as the procedure for setting the access start address in the address register A62.

Next, regarding the operation when the ROM table 12 is accessed, the data control unit address is set in the system address bus 14, the address decoder B65 is operated, and the output line 2 of the address decoder B51 is
3 is activated and gate D5, which is an AND gate,
3. Guided to gate E54 and gate F55.

If the write signal 20 is “1”, the 3-state buffer A58 is connected to the system data line 15.
The contents are transmitted to the extended data line 18, and writing is performed. Conversely, if the write signal is “0”, the 3-state buffer B59 is connected to the extended data line 18.
The contents are transmitted to the system data line and a read operation is performed.

On the other hand, the output of gate D53, which is an AND gate, becomes the access notification signal 16, which passes through OR gate G56 and becomes the clock input of address register A62. At this time, address register A6
The output of the adder 64 is applied to the data input of No. 2 via the multiplexer 61. Therefore, each time the ROM table section 12 is accessed, the contents of the address register A62 are automatically updated.

Next, another embodiment of the present invention will be described with reference to FIG. In this example, the right to use the interface RAM 30 sandwiched between two sets of control units is given to the CPUA 7 through a handshake line 31.
The operation will be explained using an example in which M words of data are transferred from CPUB 0 to CPUB 71.

Through the handshake line 31, the CPUA 70 acquires the right to use the interface RAM 30.

The “write start address” and “address addition value” are set in the address control unit 10.

Continuous writing is performed to the data control unit 11 M times.

The handshake line 31 instructs the CPU 71 to perform a data read operation.

A "read start address" and "address addition value" are set in the address control unit 10.

The data control unit 11 is read out M times consecutively.

The handshake line 31 notifies the CPUA 70 that the data read operation has been completed.

In yet another embodiment, the address addition value may be fixed (for example, "1"). In this case, address register A62 in FIG. 3 is replaced with a counter, and multiplexer 61, address register B63, and adder 64 are omitted. Also, in terms of CPU operation, there is no need to set the address addition value.

As explained above, this method has the advantage of being able to perform extended address conversion in about one third of the steps compared to the conventional method, and also realizing high-speed data transfer operations between CPUs.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing the detailed operation of the expansion section 5 according to an embodiment of the present invention. FIG. 3 is a block diagram showing details of an address control section and a data control section showing one embodiment of the present invention. FIG. 4 is a block diagram showing a modification of one embodiment of the present invention. Explanation of symbols, 1...CPU section, 2...ROM section,
3...RAM section, 4...IO section, 5...extension section, 6
... Control bus, 7 ... Address bus, 8 ... Data bus, 10 ... Address control section, 11 ... Data control section, 12 ... ROM table section (or extended data memory), 13 ... System control bus Connection line with, 14... System address bus, 15...
... Connection line with the system data bus, 16 ... Signal line that informs the address control section that the extension section has been accessed, 17 ... Extension address line, 18
...Extended data line, 19...Clock, 20...
Write signal, 21...address recorder output line,
22...Address recorder output line, 23...Address recorder output line, 50...Gate A, 51...
...Gate B, 52...Gate C, 53...Gate D (AND circuit), 54...Gate E, 55...Gate F, 56...OR gate G, 58...3-state buffer A, 59... ...3-state buffer B, 60... Address record A, 61... Multiplexer, 62... FFA (address register A), 63... FFB (address register B), 64
... Adder, 65 ... Address recorder B.

Claims (1)

[Claims] 1. An address control method for accessing an extended memory 12 connected to a central processing unit via a control bus 13, an address bus 14, and a data bus 15, wherein the extended memory has an address register 62
, address increment register 63, and both registers 6
an adder 64 for adding the contents of 2 and 63, and means 50 and 6 for setting write data on the data bus in the address register 62 when a write operation is instructed to the first specific address.
means 5 for setting write data on the data bus in the address increment register 63 when a write operation is instructed to a second specific address such as 0, 61, 51, 56;
0, 60, 52, and when reading or writing is instructed to the third specific address, the address register 6
Based on the contents set in 2, the above extended memory 1
means 65 for accessing 2 and setting the output of the adder 64 in the address register;
54, 55, 58, 59, 53, and 56, and access to continuous areas of the extended memory 12 is accessed by repeating access to the third specific address.