JPH022402A - Programmable controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a programmable controller, and particularly aims at improving the input/output pass check mechanism thereof.

[Conventional technology]

FIG. 4 shows a general configuration example of a programmable controller, in which a processor 1 and a people output module 2 are connected via an input/output bus 3.

As for the specifications of the input/output bus 3 for exchanging input/output data, a signal system as shown in Figure 5 is adopted, and the signals in the numbered part of Figure 5 have the meanings shown in the following table. It is something you have.

In such a configuration, signals are read from the manual module and signals are written from the output module at timings shown in FIGS. 6(^) and (B), respectively. However, in such a programmable controller, data access is performed as follows in order to improve input/output reliability.

First, the input module is provided with a circuit as shown in FIG. 7(A), and input data is read by the processor 1 executing the procedure shown in FIG. 7(B). In other words, input data from an external device is TEND
Step 51: The signal causes the latch circuit 211 to latch.
), energizes the output unit 212 operated by the RD signal and reads input data from the data bus. This reading is performed twice (step ζ3°SS), and the data for the two times is
(2) is compared (step S7), and if they match, the input data is confirmed (step S9), and if they do not match, the process is tried again.

Further, the output module is provided with a circuit as shown in FIG. 8(A), and output data is written by the processor 1 executing the procedure shown in FIG. 8(B).

That is, output data is set in the first stage latch 201 based on the WR flaw signal (step 5ll). After that, R.D.
The output unit 203 is operated by the signal to read out the first stage latch data (step 513), and it is confirmed that the write data and read data match (step 515).
, first stage latch data is transferred to the second stage latch 202 by the TEND signal. This becomes the output data. On the other hand, if there is a mismatch, retry is performed.

(Problems to be Solved by the Invention) However, even the above-described data access may be insufficient.

For example, consider a case where the address bus and data bus are short-circuited as shown in FIG. As shown in the figure, when address line ^4 and data line BO are short-circuited, A4="
BO is always "L" when the input module is "L", and even if the input module performs the double reading verification procedure, incorrect data will be treated as manual data.

Also, consider the case where there is a short circuit between the data buses, as shown in FIG. As shown in the figure, when the data lines BO and 81 are short-circuited, if either BO or Bl is "H" and one is L, then both BO and B1 are "L" and the 2 Even if you follow the reading verification procedure, incorrect data will end up being human data.

As mentioned above, conventional programmable controllers have
Even with the double-read verification procedure in the people counting module, there was a risk that bus short circuits could not be detected and incorrect data would be used as input/output data.

The present invention detects a short circuit between an address bus and a data bus in an input/output bus, or a short circuit between data buses, and prevents erroneous human output data from being accessed, thereby providing a highly reliable programmable controller. The purpose is to provide.

[Means for Solving the Problems] To this end, in the present invention, in a programmable controller in which a processor and a human output module are coupled via a bus line, the processor connects the human output module to data input/output. The present invention is characterized in that it includes means for detecting a short circuit in the bus line by accessing predetermined data regarding the bus line in a state where the bus line is not involved.

[For production]

In the present invention, a short circuit between the address bus and the data bus can be detected by fixing the address bus to L and reading data without inputting or outputting data to the output module, or transmitting a test pattern to the output module. Short circuits between data buses are detected by setting, reading, and verifying.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of a procedure for detecting a short circuit between an address bus and a data bus by the programmable controller of the present invention. This procedure can be adopted in a programmable controller having the configuration as shown in FIG. 4, and this procedure can be provided in a system program that the processor 1 normally has.

When this procedure starts, first in step 521, address bus signals 〇 to A4 are all set to L, and step S2
At step 3, the data on the data buses BO to 87 is read without accessing any of the outgoing modules 2. Then, in step S25, it is checked whether all the data are H. As shown in Figure 9, the data bus is pulled up to 5V, so if there is no abnormality, all read data should be H. However, if either the data bus or the address bus is If there is a short circuit, all of the address buses AO to A4 are at L, so the data bus line where the short circuit exists is at L. That is, the presence or absence of a short circuit can thereby be recognized (step S27, 529).

However, if there is no short circuit, that is, if there is no abnormality in the address bus or data bus, it is sufficient to continue operating as a programmable controller, and if a short circuit is detected, an appropriate notification such as a display or buzzer will be sent. The operator may be notified of this by some means.

In addition to short circuits between address bus and data bus,
Abnormalities such as a short circuit between the data bus and another signal line can also be checked using this procedure.

FIG. 2 shows an example of a procedure for detecting a short circuit between data buses. In this example, after sequentially writing test data for the data buses B1 to B7 to the output module farthest from the processor 1, the same read verification as that performed for the circuit in FIG. 8(A) is performed. It is for checking,
Since TEND is not set at this time, no data is output to the outside. Then, if there is no abnormality in all the data buses, it is assumed that there is no short circuit and the operation of the programmable controller is continued, and if there is any abnormality in any of the data buses, a short circuit can be detected and an appropriate notification can be made (step S4C, 549).

The test data is 8f!, in which any one bit of the data is L, as shown in FIG. You can prepare similar data and use it sequentially in the above steps.
Such test data can also be stored in the ROM of the processor 1 or the like. Then, the read data may be compared with the data shown in the third diagram. If there is a short circuit between the data buses, the write data and read data will not match, so an abnormality can be detected.

〔Effect of the invention〕

As explained above, according to the present invention, short circuits between the address bus and data bus in the input/output bus and short circuits between the data buses can be detected, so that erroneous input and output can be prevented. The reliability of the programmable controller can be improved.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an example of a procedure for detecting a short circuit between an address bus and a data bus by the programmable controller of the present invention, FIG. 2 is a flowchart showing an example of a procedure for detecting a short circuit between a data bus, and FIG. Fig. 4 is a block diagram showing a general configuration example of a programmable controller; Fig. 5 is an explanatory diagram showing test data that can be used in the procedure of Fig. 4; An explanatory diagram for explaining signals, FIGS. 6(^) and (B) are timing charts for explaining the timing of signal exchange in FIG. 5, and FIGS. 7(A) and (B) are, respectively, A block diagram showing an example of a circuit on the input module side for verifying input data and a flowchart showing an example of processing by a processor, Figures 8 (^) and (B) respectively show a circuit on the output module side for verifying output data. A block diagram showing an example and a flowchart showing an example of processing by a processor; FIG. 9 is an explanatory diagram for explaining a short circuit that occurs between an address bus and a data bus; FIG. 10 is an explanatory diagram for explaining a short circuit that occurs between data buses. FIG. 1... Processor, 2... Input/output module, 3... Input/output bus, ^0~^4... Address bus, BO~B 7-... Data bus. Figure 1 Figure 2 Figure 4 Figure 3 Figure 5 *C5 K-RDY (A) *PWT *RDY (B) Figure 6 S Figure 1 Figure 7 A.: Figure 29

Claims (1)

[Scope of Claims] 1) A programmable controller in which a processor and an input/output module are coupled via a bus line, wherein the processor is configured to operate on the bus line without involving the input/output module in data input/output. A programmable controller comprising means for detecting a short circuit in the bus line by accessing predetermined data. 2) The means reads data from the data bus constituting the bus line without accessing any input/output module, and determines whether the read data is at a predetermined logic level in the state. 2. The programmable controller according to claim 1, further comprising detection means for detecting the presence or absence of a short circuit between the address bus and the data bus constituting the bus line. 3) At least a two-stage latch is provided in an output module farthest from the processor, and the means outputs a test pattern to the output module, and after the output, reads data from the first stage latch and performs verification. ,
2. The programmable controller according to claim 1, further comprising detection means for detecting a short circuit between data buses forming the bus line.