JPH0225041A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a field effect transistor.

The purpose is to improve the performance and ensure the reliability of the gate electrode by shortening the gate length and increasing the area of the upper surface of the gate electrode.

A first insulating layer 5 is formed on the surface of the semiconductor substrate on which the active layer 3 is formed.
After forming an opening in the gate electrode forming portion of the first insulating layer, a second insulating layer 5 is formed on the entire surface of the substrate.
2 and forming a recess narrower than the opening in the gate electrode forming portion; forming a mask 63 having an opening wider than the recess on the second insulating layer; A gate electrode window 9 is formed by etching the second insulating layer using etching means having a directionality in a direction substantially perpendicular to the surface of the substrate to form an opening having a narrower width at the bottom than at the top.
4, and forming a gate electrode 9 which is buried in the gate electrode window by depositing metal almost vertically on the surface of the substrate.
and forming a metal layer 10 on the mask 63;
A method for manufacturing a semiconductor device includes a step of removing the mask and a metal layer thereon by lift-off.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a field effect transistor.

Field-effect transistors have been improved in performance by shortening the gate length.

As a high-speed field effect transistor, Si
GaA of Schottky gate using the fact that it is higher than
There are sMESFET, heterojunction FET, etc.

DCF L (Direct Coupled
FET Logic) circuits are used in integrated circuits.

FIG. 4 shows a DCFL circuit. This circuit has a normal
An on-type (D-mode) element and a normally-off-type (E-mode) element are used in pairs, and a relatively large current flows through the Schottky gate of the normally-off type element.

Therefore, when the gate length is shortened in order to improve the performance of the device, the current density of the gate electrode increases, accelerating deterioration and making it difficult to ensure reliability.

Therefore, it is necessary to take measures to ensure reliability.

[Conventional technology]

The structure of a conventional basic GaAs MESFET is shown in FIG. Figures 3(a) and (b) are respectively.

1 is a top view and a cross-sectional view, 1 is a semiconductor substrate, 3 is an active layer,
4 is an element isolation layer, 5 is an insulating layer, 7 is a source electrode, 8 is a drain electrode, 9 is a gate electrode, 11 is a gate finger,
12 represents an external terminal.

Incidentally, a current flows into the gate electrode from the external terminal 12 via the gate finger 11, and when the cross-sectional area of the gate electrode is small, the current density becomes large.

For example, in the case of a CFL circuit as shown in FIG. 4, if 2V is supplied to the 9 source electrodes, a current of 3 mA will flow to the gate electrodes. If this is converted into current density, the gate length is 0.1
In μm, it is approximately 6×10′ A/e112.

This is a fairly large value, and electric field concentration occurs in the part where current flows from the external terminal to the gate finger shown in Figure 3, which accelerates deterioration in that part and may even lead to disconnection, which is a big problem in terms of ensuring reliability. becomes.

[Problem to be solved by the invention]

Therefore, in order to shorten the gate length and reduce the current density, it is desirable to use a gate electrode with a wide top or T-shaped cross section, with a short portion in contact with the active layer and a wide top.

The present invention provides a method for manufacturing a semiconductor device having a gate electrode having such a shape.

[Means to solve the problem]

FIG. 1 is a sectional view of a semiconductor device having a gate electrode according to the present invention, and FIG. 2 shows its manufacturing process.

Means for solving the above problem will be described below with reference to the reference numerals in FIGS. 1 and 2.

A first insulating layer 5 is formed on the surface of the semiconductor substrate on which the active layer 3 is formed.
1 and forming an opening in the gate electrode formation portion of the first insulating layer, a second insulating layer 5 is formed on the entire surface of the substrate.
2 and forming a recess narrower than the opening in the gate electrode forming portion; forming a mask 63 having an opening wider than the recess on the second insulating layer; A gate electrode window 9 is formed by etching the second insulating layer using etching means having a directionality in a direction substantially perpendicular to the surface of the substrate to form an opening having a narrower width at the bottom than at the top.
4, and a gate electrode 9 buried in the gate electrode window by depositing metal almost vertically on the surface of the substrate.
and a step of forming metal NIO on the mask 63;
The above problem is solved by a method of manufacturing a semiconductor device including a step of removing the mask and the metal layer thereon by lift-off.

[Effect]

In the present invention, as shown in FIG.
The cross-sectional area can be increased by making the part in contact with the part narrower, the upper surface wider, and the height larger. Therefore, when current flows from the external terminal to the gate electrode via the gate finger, electric field concentration at the connection between the external terminal and the gate finger is alleviated. As a result, deterioration and disconnection are prevented and high reliability is ensured.

In order to realize such a structure, a mask 63 is used, which has an opening wider than the recess 92 for forming the lower part of the gate electrode, and has an opening 93 for forming the upper part of the gate electrode, the lower opening of which is larger than the upper opening. Then, anisotropic etching is performed to form a gate electrode window 94 and expose the active layer 3.

When metal is deposited on the entire surface, the flying direction of each particle is almost perpendicular to the surface, so the gate metal on the active layer and the metal layer on the mask are deposited separately.

It is easy to lift off with the metal layer placed on the mask.

Embodiment C] Hereinafter, an embodiment of the present invention will be described with reference to the manufacturing steps shown in FIGS. 2(a) to 2(i).

Refer to FIG. 2<a> 1-Buffer layer 3000 thick on GaAs semiconductor substrate 12. An active layer 3 having a thickness of 1000 layers is epitaxially grown. After that, oxygen ion 0+ is added for element isolation.
Ions are implanted to a depth of about 3,000 to create element isolation IW.
form 4.

Refer to FIG. 2(b) 4000 layers of SiO2 (or 5iON) are deposited on the entire surface by chemical vapor deposition (CVD) to form the first insulating layer 5.
form 1. Apply photoresist to the entire surface and apply the source.
A hole is made in the drain electrode forming part and a photoresist mask 6 is formed.
] to form. At this time, create a reverse taper so that the lower opening is wider than the upper opening. - Etching the first insulating layer using the mask to expose the active layer 3; Next, ohmic metal (AuGe20) is applied vertically to the entire surface.
The ohmic metal layer 62 is formed by vapor-depositing an ohmic metal layer 62.

See FIG. 2(c) Photoresist mask 61 and ohmic metal Ji on it.
When i62 is lifted off, a source electrode 7 and a drain electrode 8 of ohmic metal (8UG e 200 people/Au 3800 people) are formed on the active layer 3.

Referring to FIG. 2(d), a photoresist (not shown) is applied to the entire surface and an opening with a width of 0.8 μm is formed in the gate electrode forming area.

Anisotropic etching is performed from the opening to form a gate electrode forming opening 91 having a width of 0.8 μm in the first insulating layer.

The opening may penetrate to the surface of the active layer.

5i02 (or 5iON) is applied to the entire surface by CVD method (see Fig. 2(e)).
A second insulating layer 52 is formed by depositing 1,000 people.

Since 5i02 (or 5iON) attaches in the same direction.

It also adheres to the sides of the gate electrode forming opening 91 and has a width of 0.
A recess 92 for forming the lower part of the Day 1 electrode of about 2 μm is formed.

Referring to FIG. 2(f), a photoresist is applied to the entire surface, and an opening on the upper surface of the photoresist I.
A mask 63 having an opening 93 for forming the upper part of the gate electrode of an inverted Taper type having a width of .mu.m and a wider opening on the lower surface is formed.

FIG. 2(g) Reference: The second insulating layer 52 and the first insulating layer 51 are etched through the opening 93 for forming the upper part of the gate electrode by reactive ion etching (RIE) to expose the active layer 3 and form the gate electrode. A window 94 is formed.

Next, recess etching is performed to adjust the thickness of the active layer under the gate.

Referring to FIG. 2(h), Al as a gate metal is evaporated to a thickness of 5,000 nm over the entire surface, and a gate electrode 9 is formed on the active layer 3. Metal 1 on mask 63
form 10. This thickness is selected so that the height of the upper surface of the second insulating layer 52 and the gate electrode 9 are the same. , The mask 63 and the metal layer 10 thereon are removed by lift-off, as shown in FIG.

In this way, the upper surface of the second insulating layer 52 and the upper surface of the gate electrode 9 are aligned in height, and the gate length in contact with the active layer 3 is set to 0.2 μm.
, a field effect transistor in which the width of the upper surface of the gate electrode is 0.8 μm is realized.

〔Effect of the invention〕

As explained above, according to the present invention, the gate length can be shortened by increasing the cross-sectional area of the gate electrode.
A field effect transistor with improved performance and high reliability that can withstand large gate currents can be realized. moreover,
Since the upper layer of the element is flat, it is easy to form upper layer wiring.

The present invention greatly contributes to the development of high-speed integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device. Figure 2 shows the manufacturing process. Figure 3 shows the structure of GaAsMET. Figure 4 shows the DCFL circuit It is. In fig. 1 is a semiconductor substrate. 2 is a buffer layer. 3 is the active layer. 4 is an element isolation layer. 5 is an insulating layer. 51 is a first insulating layer. 52 is a second insulating layer. 61.63 is a mask and is a photoresist mask. 62 is an ohmic metal layer. 7 is the source electrode. 8 is the drain electrode. 9 is a gate electrode. 1 is an opening for forming a gate electrode. 2 is a recess for forming the lower part of the gate electrode. 3 is an opening for forming the upper part of the gate electrode. 4 is the gate electrode window. 0 is a metal layer. l is gate finger. 2 is external terminal ``Cross-sectional view of 4th t1'' Figure 1 Leather production process Figure 2 (Kume 1) Binding process 3) of the second caliber Manufacturing process Figure $2 (A-2) top view Detective) A-All' loaf side diagram (shi) MAL of GcLAs MESFET For $3

Claims (1)

[Claims] A first layer is formed on the surface of the semiconductor substrate (1) on which the active layer (3) is formed.
After forming an insulating layer (51) in the first insulating layer at the gate electrode formation portion, a second insulating layer (52) is formed on the entire surface of the substrate to form the gate electrode. A step of forming a recess narrower in width than the opening in the formation portion, forming a mask (63) having an opening wider than the recess on the second insulating layer, and using the mask to form a recess on the substrate surface. etching the second insulating layer using etching means having a directionality substantially perpendicular to the substrate surface to form a gate electrode window (94) having an opening narrower at the bottom than at the top; A gate electrode (9) which is buried in the gate electrode window by depositing metal almost vertically thereon, and the mask (
63) A method for manufacturing a semiconductor device, comprising: forming a metal layer (10) thereon; and removing the mask and the metal layer thereon by lift-off.