JPH04199643A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention relates to the improvement of a compound semiconductor device that uses a two-dimensional carrier gas generated in the vicinity of a heterojunction interface as a channel, and its manufacturing method. The purpose of the present invention is to provide a technology capable of forming an element isolation region having the required minute dimensions, and to provide a technology that is formed on a substrate, has a planar pattern of the element isolation region, and contains oxygen as a constituent element. a first compound semiconductor layer formed on the substrate and embedded in the insulating film so that at least a portion of its upper surface is exposed; and a second compound semiconductor layer formed on the compound semiconductor layer and containing Af.

[Industrial Application Field] The present invention relates to a compound semiconductor device that uses a two-dimensional carrier gas generated in the vicinity of a heterojunction interface as a channel, and to improvements in a manufacturing method thereof.

Currently, as this type of compound semiconductor device, for example, H
EMT (high electron mobility)
y transistor) and DMT (doped
channel MTS 1ike FET)
In recent years, research and development has been carried out to improve the performance of these transistors by selecting materials for use in them, but there are various problems that must be solved in order to realize this.

[Conventional technology]

Generally, when creating the above type of compound semiconductor device,
The GaAs layer stacked on the GaAs substrate and Af! Ga
However, in recent years, an InGaAs layer and an I nGaAs layer stacked on an InP substrate have been used.
The use of nAfAs layers can increase the concentration of two-dimensional electron gas, improve high speed, or provide high performance such as the ability to extract large currents.Therefore, active research is being conducted, and it is already at the laboratory stage. It has been realized.

FIG. 7 is a cross-sectional side view of a main part for explaining a conventional example of an InGaAs layer InAfAs HEMT.

In the figure, 1 is an InP substrate doped with iron (Fe) to make it semi-insulating, 2 is an undoped InGaAs channel layer, 3 is an n-1nAfAs electron supply layer, and 4 is an n-
GaAs1i electrode contact layer, 5 is an isolation region between elements formed by ion-implanting oxygen, 6 is A u G e
/ A u G e
8 is the gate electrode of A2, and 9 is the drain (or source) of A u Cx e / A u! The poles and 10 indicate two-dimensional electron gas layers, respectively.

[Problem to be solved by the invention]

In the HEMT shown in FIG. 7, sufficient isolation between elements cannot be achieved, and a current path is likely to be generated in the channel layer 2, as indicated by the arrow.

The reason for this is that even if oxygen ions are implanted into InGaAs, the resistance does not become high.

Another device isolation method that can be considered in such a case is a so-called high-resistance layer embedding method in which an insulating film is buried in that portion instead of oxygen ion implantation. Of course,
If this method is adopted, a recess must be formed in which to bury the high resistance layer.

However, currently LSI (large 5ca
There is no technology for etching InGaA,S and InGaAs with high accuracy in a fine size of about 1 [μm] to 2 [μm], which is required for integrated circuits.

In general, to etch InGaAs, InAP, and As, ammonia (NHZ) or sulfuric acid (H,
Although it is possible to apply the Wenoto etching method using an etchant based on So, ), it is impossible to perform etching with high precision.

FIG. 8 shows a HEMT shown in FIG. 7 to explain the case where etching is performed to form an element isolation region in the HEMT.
The same symbols as those used in FIG. 7 represent the same parts or have the same meanings.

In the figure, 11 is an n-GaAs1i electrode contact layer 4.
In the photoresist film formed above, IIA indicates an opening in the photoresist film 11, and 5A indicates a recess for burying a high resistance layer.

In this case, as is clear from the figure, the pattern is deformed due to the etching solution seeping into the interface between the n-GaAst electrode contact layer 4 and the photoresist film 11, or isotropic etching. As a result, the original pattern of the recesses 5A cannot be obtained.

In the first place, it is difficult to perform uniform wet etching over the entire surface of a wafer at the level of miniaturization required for LSI. In addition, reactive ion 0 etching (re
active ion etching (RIE)
method, since there is no enching gas available,
cannot be applied.

Needless to say, if effective isolation between elements cannot be achieved, a mutual interference effect between elements called a side gate effect will occur, leading to malfunction of the LSI.

The present invention aims to provide a technique that can form element isolation regions having minute dimensions required for LSI, regardless of the compound semiconductor material.

[Means to solve the problem]

1 and 2 are cross-sectional side views of essential parts of a compound semiconductor device at key points in the process for explaining the present invention in detail.

In the figure, 21 is an InP substrate, 22 is a mask film made of SiOz, 23 is an InGaAs layer, and 24 is an InA
l, As layer, 24A is polycrystalline InA! ! , As layers are shown, respectively.

As is clear from the figure, the InGaAs layer 2323 is St
It does not grow on the mask film 22 made of O□, and its growth selectivity is sufficiently high, but InAl! , AsN24 is Si
It is also grown on the mask film 22 made of NG, and when observed under a microscope, it becomes polycrystalline. The reason for this can be explained as follows. That is, 1 n G a A
When growing s Ji23, In and Ga are 5
The adhesion force to iOz is small, so the InGaAs layer 23 does not grow on the mask film 22 made of Sin. However, when the InAl, As layer 24 is grown, the bonding force between Al1 and 02 in the Sin is strong, and therefore, first, on the mask film 22 made of Sin,
A1 is attached and polycrystalline InAj! is formed using it as a nucleus. A
S grows. Incidentally, when the above-mentioned experiment was conducted using SiON as the material of the mask film, similar results were obtained.

As can be understood from the above experimental results, when a SiO□ film or a SiON film is used as a mask film, InGa
By utilizing the difference in selective growth properties of As and InAJ2As, it is possible to form a flat, high-resistance buried layer.
Moreover, the high-resistance buried layer can be miniaturized to the extent required for LSI.

As described above, in the compound semiconductor device and the manufacturing method thereof according to the present invention, (1) the compound semiconductor device is formed on a substrate (for example, semi-insulating 1nP substrate 31), has a planar pattern of isolation regions, and has an oxygen as one of its constituent elements (for example, the insulating film 32 made of Sin), and a second compound formed on the substrate and embedded in the insulating film so that at least a part of its upper surface is exposed. A semiconductor layer (e.g., InGaAs channel Ji34), and a second compound semiconductor layer (e.g., n-1nAj2As electron supply N35) formed on the insulating film and the first compound semiconductor layer and containing Af. or (2) in the above (1), characterized in that a compound semiconductor buffer layer is interposed between the substrate and the insulating film, or (3) in the above (1) or (i). (2) Insulation p is si
o.

or (4) in (1) or (2) above, the insulating film is made of Si.
(5) In (1) above, the first compound semiconductor layer is
nCaAs and the second compound semiconductor layer is InA.
(6) In (1) above, the first compound semiconductor layer is G.
aAs, and the second compound semiconductor layer is AEGaA.
(7) In the above (1), the first compound semiconductor layer is I.
n5b and the second compound semiconductor layer is AP.

or (8) forming an insulating film containing oxygen as one of the constituent elements on the substrate, and then patterning the insulating film into the shape of an element isolation region. Next, a step of growing a first compound semiconductor layer on the substrate except on the insulating film, and then growing a second compound semiconductor layer containing AP on the insulating film and the first compound semiconductor layer. (9) In (8) above, the method includes growing a compound semiconductor buffer layer on the substrate and then forming an insulating film.

[Function] By adopting the above means, electrical isolation between elements in a compound semiconductor device can be realized using a high-resistance insulating film, and electrical isolation due to lateral conduction through the channel layer can be realized. Mutual interference effects between elements can be substantially suppressed, and therefore, it can contribute to higher integration or higher density of compound semiconductor devices. The entire recess for forming the separation area is not required.

〔Example〕

FIGS. 3 to 6 are cross-sectional side views of essential parts of a compound semiconductor device (HEMT) at key points in the process for explaining one embodiment of the present invention, and the following will refer to these figures. Explain.

Refer to FIG. 3. Chemical vapor deposition is performed on an InP substrate 31 that has been made semi-insulating by doping Fe.
By applying the r deposition (CVD) method, an insulating film 32 made of 5iOz and having a thickness of, for example, 0.5 (μm) is formed.

By applying a resist process in photolithography, a photoresist film 33 having a pattern of isolation regions is formed.

Referring to FIG. 4, the insulating film 32 is patterned using the photoresist film 33 as a mask by applying the RIE method using CC2□F2+He as the etching gas. Note that the etching for this patterning is performed on the semi-insulating 1nP substrate 31.
automatically stops on the surface.

For example, the photoresist film 33 used as a mask for patterning the insulating film 33 is removed by immersion in acetone.

See Figure 5. Metalorganic chemical vapor deposition (metalorganic chemical vapor deposition)
chemical vapor deposition
An InGaAs channel layer 34 having a thickness of, for example, 500 (nm) is formed by applying the ion:MOCVD method.

As a result, the insulating film 32 is interlayered with the InGaAs channel layer 34, but most of its upper surface is exposed.

Referring to FIG. 6, an n-1nAj!As electron supply layer 35 and an n-C+aAsii electrode contact layer 36 having a thickness of, for example, 30 (nm:l) are sequentially formed by applying the MOCVD method.

In this case, a polycrystalline region 35A is generated in the n-1nAfAs electron supply layer 35 directly above the insulating film 32, and
A polycrystalline region 36A is generated at the n-GaAs electrode contact N36. In addition, as an n-type impurity, Si
You can use

After this, the HEMT is completed by applying conventional techniques.

In the HEMT obtained in this way, InG
Since the aAs channel layer 34 is completely separated by the layer line 432, no current path is generated between adjacent HEMTs, and the n-1nAfAs electron supply [35 and n-GaAs electrode contact layer 36 are also Since it is polycrystalline and has a high resistance, there is no need to add any further processing or configuration for isolation between elements.

In the present invention, many modifications can be made in addition to the embodiments described above.

For example, in the above embodiment, the insulating film 32 was formed directly on the semi-insulating 1nP substrate 31, but during that time, the InAfAs
Of course, a buffer layer may be interposed.

Further, in the embodiment described above, the insulating film 32 is made of Sin.

However, as mentioned above, the difference in selective growth is due to
Since it is caused by oxygen in the insulating film, 5iO
z may be replaced with SiON.

Furthermore, as mentioned above, in the conventional technology, especially In
I n Ga As / I formed on a P substrate
nAjl! Since there was a problem with the As structure, so far we have mainly discussed that problem, but the present invention
Good results can also be obtained when applied to a GaAs/AffiGaAs structure formed on an As substrate.

That is, G a As / A 42 G a As
In the system, InGaAs can be easily made to have a high resistance by implanting oxygen ions, etc.
The s/I nAj2As system has not become a serious problem. However, if the integration is to be further advanced than at present, that is, if miniaturization is to be advanced, it will be necessary to reduce the implantation depth of oxygen ions. When that happens,
Similar to the case of the InGaAs channel layer, the isolation between elements in the GaAs channel layer is a problem, so it is effective to apply the present invention. In addition, regarding materials,
It is also effective when applied to the InSb/Aj2GaSb system.

[Effects of the Invention] In the compound semiconductor device and the manufacturing method thereof according to the present invention, an insulating film having a planar pattern of the MM region corresponding to the amount of elements and containing oxygen as a constituent element is formed on a substrate, A first compound semiconductor layer is formed to bury the insulating film so that at least a portion of the upper surface thereof is exposed, and a second compound semiconductor layer containing Al is formed on the insulating layer and the first compound semiconductor layer. ing.

By employing the above configuration, electrical isolation between elements in a compound semiconductor device can be realized using a high-resistance insulating film, and electrical isolation between elements due to lateral conduction through the channel layer can be achieved. Mutual interference effects can be substantially suppressed, and therefore, it can contribute to higher integration or higher density of compound semiconductor devices. No recesses are required to form the .

[Brief explanation of the drawing]

1 and 2 are cross-sectional side views of essential parts of a compound semiconductor device at important process points for explaining the present invention in detail, and FIGS. 3 to 6 are for explaining one embodiment of the present invention. Fig. 7 is a cross-sectional side view of the main parts of a compound semiconductor device (HEMT) at key points in the process.
Fig. 8 is a cutaway side view of the main part for explaining the conventional example of Fig. 7.
FIG. 3 is a cross-sectional side view of a main part of the HEMT for explaining a case where etching is performed to form an element isolation region in the HEMT shown in the figure. In the figure, 31 is a semi-insulating 1nP substrate, 32 is a 5if
33 is a photoresist film, 34 is an InGaAs channel layer, and 35 is n-1nAf! As
Electron supply layer, 35A is a polycrystalline region, 36 is n-GaAs
The l1 pole contact layer, 36A, each indicates a polycrystalline region. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - 23: Cutaway side view of essential parts of compound semiconductor device with 1nGaAs layer Figure 1 24: Steps to explain the principle of 1nAJAs layer Figure 2: A cut-away side view of the main parts of the compound semiconductor device, showing important parts. Fig. 4: Cutaway side view of a main part of the compound semiconductor device at key points in the above section for explaining the embodiment Fig. 5: n-GaAs electrode contact layer 1. Key points for explaining an example (Figure 6: Cutaway side view of main parts of compound semiconductor device)

Claims (1)

[Scope of Claims] (1) an insulating film formed on a substrate and having a planar pattern of an element isolation region and containing oxygen as one of its constituent elements; a first compound semiconductor layer buried so that at least a portion of its upper surface is exposed; and a second compound semiconductor layer containing Al and formed on the insulating film and the first compound semiconductor layer. A compound semiconductor device characterized by: (2) The compound semiconductor device according to claim 1, characterized in that a compound semiconductor buffer layer is interposed between the substrate and the insulating film. (3)
3. The compound semiconductor device according to claim 1, wherein the insulating film is SiO_2. (4) The compound semiconductor device according to claim 1 or 2, wherein the insulating film is SiON. (5) The compound semiconductor device according to claim 1, wherein the first compound semiconductor layer is made of InGaAs and the second compound semiconductor layer is made of InAlAs. (6)
2. The compound semiconductor device according to claim 1, wherein the first compound semiconductor layer is made of GaAs and the second compound semiconductor layer is made of AlGaAs. (7)
2. The compound semiconductor device according to claim 1, wherein the first compound semiconductor layer is made of InSb and the second compound semiconductor layer is made of AlGaSb. (8)
forming an insulating film containing oxygen as one of the constituent elements on the substrate; patterning the insulating film in the shape of an element isolation region; The method comprises the steps of growing a first compound semiconductor layer, and then growing a second compound semiconductor layer containing Al on the insulating film and the first compound semiconductor layer. A method for manufacturing a compound semiconductor device. 9. The method of manufacturing a compound semiconductor device according to claim 8, further comprising the step of growing a compound semiconductor buffer layer on the substrate and then forming an insulating film.