JPH0226021A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To facilitate diffusion of impurity in a self-alignment manner and simplify the manufacturing process by a method wherein electrode windows are formed on impurity diffused layers and a double-layer film composed of a polycrystalline silicon film and a metal silicide film is patterned by a photoetching method to form electrode patterns. CONSTITUTION:In order to connect polycide electrodes to impurity diffused layers which are a P<+>-type diffused layer 14 and an N<+>-type diffused layer formed on a substrate 1 and lead them out, a thin polycrystalline silicon film 15 is built up on the surface including electrode contact windows A formed on the impurity diffused layers 14 and 15 and the impurity is diffused into the polycrystalline silicon film 15 from the impurity diffused layers 13 and 14 by a heat treatment. A tungsten silicide film 5, which is a metal silicide film, is built up superposing the polycrystalline silicon film 15 and a double-layer film composed of the polycrystalline silicon film 15 and the tungsten silicide film 5 is patterned by a photoetching method to form electrode patterns. With this constitution, the impurity is diffused in a self-alignment manner, so that the manufacturing process can be substantially simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming electrodes of a semiconductor integrated circuit device.

Conventional technology Traditionally, aluminum alloys have been mainly used for wiring in semiconductor integrated circuit devices, but with the need for high-density wiring and multilayering, wiring materials that can withstand high temperatures have become necessary in place of aluminum. .

Therefore, a conventional aluminum alloy is used for the upper layer of the multilayer wiring, and a heat-resistant wiring material is used for the lower layer wiring. Conventionally, based on this idea, a wiring structure (hereinafter referred to as polycide) in which a polycrystalline silicon film and a metal silicide (e.g., tungsten silicide, molybdenum silicide, etc.) are layered in layers has been used for the lower wiring. .

Although polycide wiring has considerably higher wiring resistance than aluminum, it has great advantages such as heat resistance, ease of processing, and ease of miniaturization.

The conventional semiconductor integrated circuit device related to wiring will be explained with reference to FIG. 3, taking tungsten polycide wiring as an example. Figures 3(a) and 3(b) are partial structural cross-sectional views showing the steps of the conventional manufacturing process, and are based on the Digest of Technical Paper published by Saito et al.
est of Tech, Papers, ) P,
252 (1985), only the wiring portion of the semiconductor device is shown. In FIG. 3, 1 is a P-type silicon substrate, 2 is a sub-diffusion layer, 3 is an interlayer insulating film made of a silicon dioxide film, A is an opening, 4 is a polycrystalline silicon film, and 5 is a tungsten silicide film.

To briefly explain the conventional manufacturing method, as shown in FIG. 3(a), first, arsenic ions are implanted into a P-type silicon substrate 1 using an ion implantation method. A diffusion layer 2 is formed, an interlayer insulating film 3 made of a silicon dioxide film is deposited thereon, and an opening A is provided in the interlayer insulating film 3 by photolithography. Next, Figure 3 (b
), a polycrystalline silicon film 4 is deposited on the interlayer insulating film 3 including the opening A. Then, phosphorus is deposited on this polycrystalline silicon film 4 and is diffused to connect with the first diffusion layer 2 . A tungsten silicide film 5 is deposited thereon, and a polycide film electrode pattern consisting of the polycrystalline silicon film 4 and the tungsten silicide film 5 is formed by photolithography. An electrode is taken out from the first diffusion layer 2 through the opening A by polycide wiring.

This conventional method is limited to the connection between the N+ diffusion layer and the N-type polycrystalline silicon film. Similarly, ohmic contact between the dopant diffusion layer and the P-type polycrystalline silicon film is possible, but this is applicable only when the impurities in the impurity diffusion layer and the polycrystalline silicon film are of the same conductivity type.

Problems to be Solved by the Invention As described above, in the conventional method, after depositing the polycrystalline silicon film 4, phosphorus is deposited on the polycrystalline silicon film 4. To make contact with diffusion layer 2? The electrode could only be extracted from the diffusion layer. In a CMOS integrated circuit device, it is necessary to take out electrodes from both the P+ diffusion layer and the N+ diffusion layer.
, Papers, P, 252 (1985), etc., it is used only in a very limited range, where the electrode is taken out only from the zo-diffusion layer.

Furthermore, although it is possible to partially diffuse boron into the polycrystalline silicon film in order to take out the electrode from the diffusion layer, the process becomes quite complicated and is difficult to put into practical use. There are many restrictions when using a polycide film as a wiring layer in this way.

The present invention solves the above-mentioned problems, and is a multilayer wiring structure in which electrodes made of a double film of a polycrystalline silicon film and a metal silicide can be easily formed in each diffusion layer, regardless of the conductivity type of the impurity diffusion layer. The object of the present invention is to provide a forming method.

Means for Solving the Problems In order to solve the above-mentioned problems, the method for forming a multilayer wiring according to the present invention includes a method for forming a multilayer wiring in which, when connecting and taking out a polycide electrode from an impurity diffusion layer formed on a substrate, A thin polycrystalline silicon film is deposited, including the electrode connection window opened by the process, and impurities are diffused from the impurity diffusion layer into the polycrystalline silicon film by heat treatment, and metal silicide is superimposed on this polycrystalline silicon film. is deposited, and an electrode pattern is formed from this double film of polycrystalline silicon film and metal silicide by photolithography.

Effect: With the above configuration, electrode connections can be easily made using polycide wiring from both the vias and diffusion layers formed on the substrate, eliminating the need for selective ion implantation into the polycrystalline silicon film using a complicated mask process. This makes it possible to diffuse impurities into the connection surface in a self-aligned manner, making it possible to apply it to multilayer wiring in CMO3 integrated circuit devices.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows the P and ? FIG. 2 is a partial structural sectional view showing an example of connection from the diffusion layer to the electrode, and FIG. 2 is a diagram showing the procedure. In FIG. 1, 1 is a P-type silicon substrate, 11 is an N-well portion, and 13 is a P-type silicon substrate.
, 14 respectively? and a P diffusion layer, a device isolation region separating them, 3 an interlayer insulating film, a polycrystalline silicon film, and 5 a tungsten silicide film.

The manufacturing procedure for the above configuration is as follows.

In FIG. 2(a), an N-well portion 11 is formed on a P-type silicon substrate 1, and an element isolation region is formed on the surface of the substrate including the N-well portion to form an impurity diffusion layer. The diffusion layer opening and the diffusion layer 14 are formed separately.

Next, in FIG. 2(b), an interlayer insulating film 3 made of a silicon dioxide film is deposited. Next, in FIG. 2(C),
Windows A for electrode connection are formed in the N+ diffusion layer U and the P+ diffusion layer 14 by photolithography.

Next, in FIG. 2(d), a polycrystalline silicon film is deposited on the surface including the window A, annealed at a temperature of 900°C, and arsenic (or phosphorus) is deposited from the N diffusion layer and the P diffusion layer 14. ), and boron is rapidly diffused into the polycrystalline silicon film to establish conduction between the polycrystalline silicon film and these diffusion layers 13 and 14. If the polycrystalline silicon film thickness is 1000A or less,
It is possible to establish conduction through heat treatment. This polycrystalline silicon film is used to improve the adhesion of the metal silicide deposited thereon to the base, and is effective at about 100A.

Therefore, the practical polycrystalline silicon film thickness is 100A~
It is in the range of 1000A. Next, after removing the thin oxide film formed on the surface of the polycrystalline silicon film, as shown in Figure 2 (
In e), a tungsten silicide film 5 is deposited as a metal silicide to a thickness of 2000 Å. Next, in Figure 2 (0
In this step, an electrode pattern is formed from a double film of a polycrystalline silicon film and tungsten silicide A5 by photolithography. After forming the electrode pattern, the tungsten silicide film 5 is annealed, which can also serve as the heat treatment described above.

In this structure? The P+ diffusion layers 13 and 14 are connected to the contact id film 5. Although the polycrystalline silicon film on the interlayer insulating film 3 is not doped, the effect on wiring resistance is small. Further, the same effect can be applied to other metal silicides, such as molybdenum silicide films.

In the conventional method, the electrode is taken out from the impurity diffusion layer in the polycrystalline silicon film with P+ and ? It was necessary to selectively introduce impurities corresponding to each diffusion region of The process can be significantly simplified. The contact resistance of the electrodes at this time is almost the same as in the conventional method. Further, the resistance of the wiring portion increases due to the high resistance of the polycrystalline silicon film, but since the metal silicide is as low as 4 to 50, the effect can be ignored in practical terms.

Although omitted in this embodiment, the electrodes taken out from the polycrystalline silicon gate can be connected in the same manner as described above.

Effects of the Invention As described above, according to the present invention, when forming an electrode from an impurity diffusion layer, two layers of polycrystalline silicon film and metal silicide are used.
The heavy film electrode is independent of the conductivity type of the impurity diffusion layer
It can be easily formed in the respective diffusion layers of + and gadfly. Therefore, conventionally, achieving this required a complicated manufacturing process, but now it is possible to diffuse impurities from the impurity diffusion layer into the polycrystalline silicon film in a self-aligned manner, which reduces the complexity of the manufacturing process. The multilayer wiring structure, which was conventionally only used for special wiring, can now be used for the wiring of CMO5 integrated circuit devices, and its industrial value is extremely large.

[Brief explanation of the drawing]

1 is a cross-sectional view of a partial structure of a semiconductor device obtained by a method for forming multilayer wiring according to an embodiment of the present invention, FIG. (a),
(b) is a sectional view showing a conventional forming method. l... P-type silicon substrate, 3... interlayer insulating film, 5.
...Tungsten silicide film, 11...N well part, identification...element isolation region, mouth...N diffusion layer, 14...
・P diffusion layer, ■...polycrystalline silicon film.

Claims (1)

[Claims] 1. A step of forming an interlayer insulating film on the main surface of a semiconductor substrate having an impurity diffusion layer, and forming an electrode connection window in the impurity diffusion layer by opening a hole in the interlayer insulation film, including the electrode connection window. a step of depositing a thin polycrystalline silicon film, a step of diffusing impurities into the polycrystalline silicon film from the impurity diffusion layer formed on the substrate by heat treatment, and depositing a metal silicide superimposed on the polycrystalline silicon film. and forming an electrode pattern from the double film of the polycrystalline silicon film and metal silicide by photolithography.