JPH0226036A - Junction-type field effect transistor - Google Patents

Abstract

PURPOSE:To improve withstand voltage between a source and a drain by providing a first gate area on the bottom surface of a first gate opening formed on the surface of an epitaxial layer. CONSTITUTION:Opposite conductive type first and second gate areas 6G and 7G are provided on the upper layer of an epitaxial layer 2 formed on the surface of a semiconductor substrate 1 and the first gate area 6G is provided on the bottom surface of the first gate opening part 6 formed on the surface of the epitaxial layer 2. Then, an oxide film 3 is masked and etching is performed to a specified depth of the epitaxial layer by reaction ion etching and the first gate area 6G is formed deeply to form the first gate to a specified depth without performing treatment at high temperature. It allows the depth of source and drain to be shallow and improves withstand voltage between the source and the drain.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a junction field effect transistor.

[Conventional technology]

With the recent expansion of applications of dual-gate junction field effect transistors, there has been a desire for improved source-drain withstand voltage characteristics.

FIGS. 3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for manufacturing a junction field effect transistor.

First, as shown in FIG. 3(a), a p-type silicon substrate 1
n-type epitaxial layer on the surface of 2. is grown to a thickness of 2 to 5 μm, and a silicon oxide film 3a is grown on the surface thereof.

Next, a source opening 4 and a drain opening 5 are provided using photolithography, and the epitaxial layer 2. A source region 4s and a train region 5o are respectively formed from the surface to the inside.

Next, as shown in FIG. 3(b), after thermally oxidizing the surface, a first gate opening part 6a is provided in the first gate formation region using photolithography technology, and the first gate opening part 6a is formed in the first gate formation region by p-type diffusion. , form.

Furthermore, as shown in FIG. 3C, the opening 6a is thermally oxidized, and then an n-type second gate region 7G is formed using photolithography.

Next, as shown in FIG. 3(d), contact windows are formed on the bottom surfaces of each of the openings 4.5 and 61 by photolithography, and contact windows are formed on the surfaces thereof including the second gate opening 7, for example. An aluminum layer with a thickness of 1 to 3 μm is formed by vapor deposition or sputtering, and a source electrode S, a first gate electrode G++, a second gate electrode G2, and a drain electrode are formed at predetermined locations using photolithography.

After that, a source electrode layer 12 was formed on the back surface.

Although not shown, the source electrode S and the second gate electrode G2 are connected to the source electrode layer 12 on the back surface as shown by the dotted line via a punched diffusion layer.

FIG. 4 is an equivalent circuit diagram of the semiconductor chip of FIG. 3(d).

A dual-gate junction field-effect transistor consists of two field-effect transistors Q1 and Q2 connected in cascade through a node M, and the drain current I
DSS is determined by transistor Q+ with input gate g1.

Transistor Q2 has a gate-source reverse voltage VGSfo
Since it is designed as a normally-on type with a large rfl, this capacitance is small and the drain-source capacitance in series with the capacitance of the transistor Q1 can be reduced.

Since each of these electrodes has a low resistance, it has the effect of improving high frequency characteristics.

[Problem to be solved by the invention]

In the conventional junction field effect transistor described above, microfabrication is performed when forming the first and second gates, so it is difficult to form an opening for a short gate length in the gate region. First, the source/drain regions are formed, then the first gate and the second gate are formed, and then the first gate is formed.
Then, the thin oxide film on the second gate was etched over the entire surface for several minutes to form first and second gate openings.

However, because of this, the depth of the source/drain region is deeper than the gate region, and the inside of the depletion layer is not secured, so that the train/source breakdown voltage is determined by the BVnss drain region and it is difficult to obtain a voltage higher than about 20V.

An object of the present invention is to provide a junction field effect transistor with high source-drain breakdown voltage.

[Means to solve the problem]

The junction field effect transistor of the present invention includes an epitaxial layer of one conductivity type formed on one surface of a semiconductor substrate of a negative conductivity type, and first and second epitaxial layers of opposite conductivity type provided on the epitaxial layer. In a junction field effect transistor having a source region and a drain region of one conductivity type formed on both sides of a gate region, the first gate region is connected to a first gate opening formed on the surface of the epitaxial layer. It is configured to be provided on the bottom surface of the hole.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

A dual-gate junction field effect transistor has a first
As shown in Figure (d), an n-type epitaxial layer 2 is formed on the surface of a p-type silicon substrate 1, and a source hole 4 and a drain hole 5 are formed on both sides of an overlying silicon oxide film 3.
A second gate opening 7 is provided on the silicon oxide film 3 sandwiched between a source region 4s and a drain region 5D formed by n+ diffusion in the n-type epitaxial layer 2, and both head regions 55 and 5D. The second gate region 7° is formed by p-type diffusion in the type epitaxial layer 2, and the first gate is opened to the middle layer of the silicon oxide film 3 and the n-type epitaxial layer 2 between the second gate region 7G and the source region. The first gate region 6G is formed in the epitaxial layer 2 surrounding the opening 6.

A source electrode S, a first gate electrode G1. A second gate electrode G2 and a train electrode are formed, and the source electrode S and the second gate electrode G2 are electrically connected to the source electrode layer 12 on the back surface as shown by the dotted line β through a punched diffusion layer (not shown). There is.

The equivalent circuit is a series configuration of two field effect transistors q1 and q2 via a node m, similar to the equivalent circuit of FIG.

Next, a method for manufacturing a junction field effect transistor will be explained.

As shown in FIG. 1(a), an n-type epitaxial layer R2 is formed to a thickness of 2 to 5 μm on a p-type silicon substrate 1, and a silicon oxide film 3 is grown to a thickness of several hundred nm by thermal oxidation. The source and drain openings 4
and 5 are provided to form n+ type source and drain regions 4s and 'in, respectively, by diffusion.

Next, as shown in FIG. 1(b), after thermal oxidation, a first gate opening 6 is provided in the first gate formation region between the source and drain regions using photolithography, and then, for example, ( Reactive ion etching is performed using 112 or dilute HF to etch the epitaxial layer 2 to a predetermined depth without increasing the gate length.

For information on high aspect ratio pattern dry etching that can be used in this process, see Semiconductor World, 12th
It is described in detail on pages 5 to 146 (1987°7).

Next, from the first gate opening 6 to the p-type first gate region 6
is formed by diffusion or ion implantation.

Thereafter, as shown in FIGS. 1C and 1D, a junction field effect transistor is formed in the same steps as the conventional steps shown in FIGS. 4C and 4D.

The distances a, b, c and d between the bottoms of the source, first gate, second gate and drain regions 4s, 6o, 7o and 5D and the n-type silicon substrate 1 are 2.5 and 1, respectively.
, 1.5 and 2.5 μm, and the first gate region 6
Since the distance 1b from G is the minimum, the controllability of the depletion layer is good.

Here, due to the manufacturing method described above, the distance p1d can be designed independently of b, so d can be set large, and the thickness of the depletion layer can be ensured sufficiently, so that the source/drain breakdown voltage can be improved! 3voss can be set to 30V.

FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

The junction field effect transistor has a second gate region 7. This is the same as the junction field effect transistor of the first embodiment except that it is different from the second gate region 7G.

In the manufacturing process, a semiconductor chip is formed using the same method as shown in FIGS. 1(a) and 1(b).

Next, as shown in FIG. 2(a), a second gate opening 7. is formed in the second gate formation region of the silicon oxide WA3 using photolithography. is opened, and then reactive ion etching is performed using the oxide film as a mask to form the epitaxial layer 2. in the same manner as in the step of forming the first gate region 6G. The second gate region 7. is etched to a predetermined depth from the surface of the second gate region 7. form.

As a result, the second gate region 7. Also, a predetermined depth can be obtained without high-temperature heat treatment, and the second gate region 7II
While the distance C1 between the drain region 5D and the silicon substrate 1 can be made smaller, the depth of the drain region 5D can be made shallower, and therefore the distance M can be made smaller.
d can be increased, and the withstand voltage 13voss between the train and the source can be improved.

〔Effect of the invention〕

As explained above, the present invention provides a junction field effect transistor in which when forming the first gate region, the source and
After forming and thermally oxidizing the drain region, use photolithography to create openings at predetermined positions, and use the oxide film as a mask to perform reactive ion etching to a predetermined depth in the epitaxial layer. By finding and forming the first gate region, the first gate can be formed at a predetermined depth without performing high-temperature processing.

Therefore, the depth of the source and drain becomes shallower, and the controllability of the first gate is improved and the withstand voltage between the source and drain can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIGS. FIG. 3 (a) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining an example
) to (d) are cross-sectional views of semiconductor chips shown in order of steps to explain an example of a conventional method for manufacturing a junction field effect transistor, and FIG. 4 is an equivalent circuit diagram of the semiconductor chip of FIG. 3(d). It is. 1...p-type silicon substrate, 2.2. ... N-type epitaxial layer, 4s... Source region, 5o... Drain region, 6... First gate opening, 6G... First gate region, 7, 71... Second Gate opening, 7G, 7
□...Second gate region.

Claims (1)

[Claims] An epitaxial layer of one conductivity type formed on one surface of a semiconductor substrate of one conductivity type, and first and second gate regions of opposite conductivity types provided on the upper layer of the epitaxial layer, formed on both sides of the epitaxial layer. In a junction field effect transistor having a source region and a drain region of one conductivity type, the first gate region is provided at the bottom of a first gate opening formed on the surface of the epitaxial layer. Characteristics of junction field effect transistors.