JPH022682A - Manufacture of grooved gate mos fet - Google Patents

Abstract

PURPOSE:To decrease overlap capacity between a gate and source/drain regions and to provide a MOS FET operable at high speed, by forming a groove in a gate section on a semiconductor substrate, forming diffused layers on the opposite sides of the groove as source and drain regions, and then performing gate oxidation for forming a gate oxide film on the inner walls of the groove. CONSTITUTION:A groove 25 is formed in a gate section on a semiconductor substrate 21 and diffused layers 26 are formed on the opposite sides of the groove 25 as source and drain regions. Then, heat oxidation is performed to produce a gate oxide film 27 such that a thickness thereof is large on the inner walls of the groove except the region close to the bottom of the source and drain regions. A gate electrode 28 is then formed within the groove 25 so as to fill the space surrounded by the gate oxide film 27. More particularly, As is implanted in a polysilicon layer 24 deposited on the P-type silicon substrate 21 and then the groove 25 is formed in the gate section. The structure is annealed within the atmosphere of nitrogen and the diffused layers 26 are formed on the opposite sides of the groove 25 as source and drain regions. Then, gate oxidation is performed to produce the gate oxide film 27 on the surface of the polysilicon layer 24 as well as on the inner walls of the groove 25.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention is based on MO3P [! T, especially Mizohori gate type MO
5F [! The present invention relates to a method for manufacturing T.

(Prior art) In order to improve the degree of integration and operation speed of integrated circuits using MOS FETs, we have developed
The gate length of PET has been increasingly reduced in recent years.

MOS F [! As the gate length of T becomes shorter, the threshold voltage changes due to the short channel effect due to variations in the gate length, and the source voltage increases regardless of the gate voltage.
Problems such as punch-through, where current flows due to the voltage difference between the drains, arise. In order to avoid these short channel effects and bunch-through in fine MO5PET,
It is necessary to reduce the source/drain junction depth Xj.

Is it possible to increase the bonding depth Xj to its maximum limit, that is, to Xj ~ Otrm? As an IO3PET structure, the literature Japanese Journal of Applied Physics (Japanese Journal of Ap
plied Phy.

5ics) 16 (1977) Sablement (Su
There is a trench gate type MOS 1'ET disclosed in PPLEMENT) 161 and PP179 to 183.

FIG. 3 shows a conventional method for manufacturing a trench gate type MOS FET. The conventional manufacturing method will be explained in order below with reference to this figure.

First, as shown in FIG. 3 (at), a silicon substrate 1 is thermally oxidized to form a SiO□ layer 2 of approximately 3000A4 on the surface.A window 3 is opened in the SiO□ layer 2 by a normal photolithography and etching process. .

Next, a polysilicon layer 4 for forming source/drain regions is coated with LPCvD over the entire surface as shown in FIG.
It is deposited on approximately 3000A4 by method.

Thereafter, a gate portion 45 is formed on the polysilicon layer 4 and the silicon substrate 1 by ordinary photolithography and etching, as shown in FIG. A gate oxide film 6 is formed to a thickness of, for example, about 200 mm on the surface of 4. Thereafter, about 3000 mm of polysilicon is deposited by the LPCVD method, and the polysilicon is patterned by ordinary photolithography and etching. A gate electrode 7 is formed inside the gate oxide film 6 and buried in the groove 5 .

After that, impurities (As,
P, B, etc.) are implanted into the polysilicon layer 4 for source/drain formation by ion implantation technology, and then annealed at a temperature of about 900 to 1000°C to form ions into the polysilicon layer 4. While activating the implanted impurity, the polysilicon layer 4
The impurity is diffused into the silicon substrate l from inside by solid phase diffusion, and as shown in Fig. 3 (d+), the groove bottom surface (gate bottom surface) is
Diffusion layers 8 as source/drain regions are formed in the substrate 1 so as to align the bonding positions.

Thereafter, as shown in FIG.
form 0.

(Problem to be Solved by the Invention) However, in the trench gate type MO3FET manufactured as described above, the sidewalls of the gate electrode 7 in the trench 5 are exposed through a thin SiO□ film called the gate oxide film 6. The structure is such that it is coupled to the source/drain region (diffusion layer 8). Therefore, the MOS FET has no choice but to have a large overlapping capacitance between the gate and source/drain regions. The overlap capacitance acts as a mirror capacitance in circuit operation, and therefore,
The large overlap capacitance between the gate and source/drain regions results in a transistor structure with large parasitic capacitance. Therefore, a fine MO3PET for high-speed operation has the disadvantage of increased overlap capacity.

In order to make the above-mentioned trench gate type MO3FET into a high-speed operation MO3FET, this invention
Mizohori ligated MO5F reduces the overlap capacitance with the drain region [! The purpose of the present invention is to provide a method for manufacturing T.

(Means for Solving the Problems) The present invention is a method for manufacturing a trench gate type MO5FET, in which a trench for a gate portion is formed in a semiconductor substrate, and diffusion layers as source/drain regions are formed on both sides of the trench. Thereafter, thermal oxidation is performed to form a gate oxide film on the inner wall of the trench.

(Function) When a groove for the gate part is formed in a semiconductor substrate and diffusion layers are formed as source/drain regions on both sides of the groove, the diffusion layer surface is exposed on the sidewalls of the groove, becoming a high impurity concentration surface, and the groove is exposed. At the bottom, the substrate surface is exposed and becomes a low impurity concentration surface. Therefore, when a gate oxide film is formed on the inner wall of the trench by thermal oxidation, the gate oxide film is thicker on the trench sidewalls than on the bottom surface of the trench, as shown in FIG. A gate oxide film is formed.However, since the area near the trench bottom circled in FIG. Oxidation II
! The thickness becomes thinner.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a manufacturing process diagram showing an embodiment of the present invention, and N
An example of hos FET creation is shown below.

First, as shown in FIG. 1 (al), a P-type silicon substrate 21
SiO□ layer 2 with a thickness of about 3000 layers is formed on the surface by thermal oxidation.
2 Do all 22. Then, a desired window 23 is opened in the entire SiO□ layer 22 by an oxidation etching process.

The substrate region exposed by this window 23 is a transistor formation region. L is applied to the entire surface including this transistor formation region.
A polysilicon layer 24 is deposited to a thickness of about 3,000 layers using the PCVD method. Then, As, which is an impurity for forming source/drain regions, is implanted into this polysilicon layer 24.

The dose amount is approximately 1, Ox to''/c++1.

Next, in the transistor formation region, in the portion that will become the gate region, the polysilicon layer 24 and the silicon I+ff
At 12t, a gate portion N25 is formed by normal photolithography and etching as shown in the first image. At this time,
Etching can be performed on both the polysilicon 1ii24 and the silicon substrate 21 using an RIE apparatus using the same gas. Thereafter, annealing is performed in a nitrogen atmosphere at 900°C to 1000°C.

Then, the impurities in the polysilicon layer 24 are activated, and at the same time, the silicon substrate 2 is removed from the polysilicon layer 24.
Impurities are diffused into the silicon substrate 21 by solid-phase diffusion, and diffusion layers 26 as source/drain regions are formed in the silicon substrate 21 on both sides of the trench 25 in the transistor formation region. At this time, the annealing time and temperature are controlled so that the bonding surface (bottom surface of the diffusion layer 26) is flush with the bottom surface of 'a25.

Next, dry Ox at a temperature of about 900℃ from goo℃.
Gate oxidation is performed in an atmosphere of 1 to form gate oxidation [27] on the surface of polysilicon layer 24 and the inner wall of N25, as shown in FIG. At this time, gate oxidation n9
27 is formed thicker on the surface of the polysilicon layer 24 and on the sidewalls of the llI 25 than on the bottom surface of the groove 25.

Figure 2 shows each dose (As; J, 2 x 10
”～Non-doped silicon base (anti-(900℃, 3
0 minutes.

N2 annealing was performed) in a dry O2 atmosphere.
It shows the experimental results of measuring the thickness of the oxidized layer at each oxidation temperature when oxidized for 0 minutes. From FIG. 2, it can be seen that the larger the dose, the thicker the oxide film formed at the same temperature becomes. Furthermore, the dose amount is 1.2×10 eyes/c.
j, 3. Ox 10”7cm (D case, 800'C
.

It can be seen that at 850°C, a peculiar phenomenon is observed in which the oxide film thickness becomes thicker than at 900°C. 850℃ dry O! Now, on a non-doped silicon substrate, the oxide film 100 is
It can be seen that an oxide film with a thickness of 1400 people is formed on a 1:2×10”/cJ doped silicon substrate, which is actually 14 times as thick as that of a person.A similar phenomenon occurs even when phosphorus is used as an impurity. being observed.

Therefore, in Figure 1 (C1), if gate oxidation is performed by about 200 people at 850°C dry 0.
As seen from the data in the figure, the bottom surface of the trench 25 is the substrate surface and has a low impurity concentration, so a gate oxide film 27 of about 200 layers is formed like normal gate oxidation, but the surface of the polysilicon layer 24 and the trench Since the sidewalls of the gate oxide 25 are high concentration layers of As formed by the polysilicon layer 24 and the diffusion layer 26, a gate oxide film 27 having a thickness of approximately 1,500 layers is formed.

Therefore, the overlapping capacitance between the gate electrode and the source/drain region (diffusion M26), which will be described later, can be reduced. Looking at the thickness of the gate oxide film on the side wall of the groove 25 in more detail, Fig.
The vicinity of the groove bottom circled in 11.1 is a junction-type region, and is a region where the impurity concentration drops rapidly, so the oxide film thickness in this portion (near the junction) becomes thinner.

Therefore, no offset (gap) occurs between the edge (inner end) of the source/drain region and the bottom edge (bottom end) of the gate electrode.

Next, gate polysilicon is deposited in the same manner as in a normal process, and the gate polysilicon is patterned in a normal photolithography and etching process to form a pattern shown in FIG.
As shown in FIG. 2, a gate electrode 28 is formed inside the gate oxide film 27 so as to fill the trench 25. At this time, unnecessary portions of the gate oxide film 27 are also removed by etching.

Thereafter, the usual steps are performed to deposit an intermediate insulating film and form aluminum wiring.

Note that in the above manufacturing method, the polysilicon layer 24 does not play a wood-like role, and therefore, a groove may be directly formed in the substrate 21 or a diffusion layer may be formed by introducing impurities. As an impurity, P as a base of As can also be used. From the experimental results shown in Figure 2, the Dawes River should preferably be 3.0 x 10" 7 cm or more.

(Effects of the Invention) As detailed above, according to the manufacturing method of the present invention, a gate oxide film that is 10 times or more thicker than usual is formed on the trench side wall portion of the gate portion by utilizing the difference in impurity concentration. This makes it possible to significantly reduce the overlapping capacitance between the gate and source/drain regions to, for example, 710 or less compared to the conventional method.

Furthermore, even if the gate oxide film on the trench sidewalls can be made thicker, t-
The trench sidewall near the bottom of the source/drain region is a region where the impurity concentration is rapidly reduced, and the oxide film thickness at the bottom of this sidewall can be made as thin as the normal gate oxide film. An offset (gap) between the edges of the region and the bottom edge of the gate electrode can be eliminated. As shown above, the overlapping capacity can be reduced (and offset).

Therefore, even if the MOS FP is of the Mizohori ligate type, it is possible to manufacture MOS FPs and Ts that can operate at high speed.

[Brief explanation of the drawing]

Is Fig. 1 the Mizohori ligate type of this invention? A process cross-sectional view showing an example of an IO3FET manufacturing method, Fig. 2 is an oxide film thickness characteristic diagram when a silicon substrate is oxidized at various doses, and Fig. 3 is a conventional trench gate type MO5F ['T FIG. 3 is a process cross-sectional view showing a manufacturing method. 21...P-type silicon substrate/plate, 25...groove, 26...
...Diffusion layer, 27...Gate oxide film, 28...Gate upper electrode. a3 keyed 81 soldiers 1. ) Shizuku rqt 1st soil? ]Figure 2

Claims (1)

[Claims] (a) A step of forming a groove for a gate portion in a semiconductor substrate and forming a diffusion layer as a source/drain region on both sides of the groove; (b) After that, by performing thermal oxidation, (c) forming a gate oxide film on the inner wall of the trench, except for the area near the bottom of the source/drain region; (c) then filling the trench inside the gate oxide film to form a gate electrode; 1. A method for manufacturing a trench gate type MOSFET, comprising the step of forming a trench gate type MOSFET.