JPH02260604A - Lamination type varistor - Google Patents
Lamination type varistorInfo
- Publication number
- JPH02260604A JPH02260604A JP1082636A JP8263689A JPH02260604A JP H02260604 A JPH02260604 A JP H02260604A JP 1082636 A JP1082636 A JP 1082636A JP 8263689 A JP8263689 A JP 8263689A JP H02260604 A JPH02260604 A JP H02260604A
- Authority
- JP
- Japan
- Prior art keywords
- end surface
- gaps
- electrode
- internal electrode
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003475 lamination Methods 0.000 title description 2
- 239000000919 ceramic Substances 0.000 claims description 16
- 238000007747 plating Methods 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 3
- 230000007850 degeneration Effects 0.000 abstract 1
- 238000009795 derivation Methods 0.000 description 17
- 230000006866 deterioration Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000006104 solid solution Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
Landscapes
- Thermistors And Varistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電圧非直線性抵抗として機能する積層型バリ
スタに関し、特に内部電極の変質を防止してバリスタ特
性の悪化を回避できるとともに、もれ電流を低減して部
品の信顧性を向上できるようにした構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer varistor that functions as a voltage nonlinear resistor, and in particular can prevent deterioration of varistor characteristics by preventing deterioration of internal electrodes. This invention relates to a structure that reduces stray current and improves reliability of parts.
一般に、バリスタは、印加電圧に応じて抵抗値が非直線
的に変化す・る抵抗体素子であり、このようなバリスタ
として、従来、第6図に示すような直方体状の積層型バ
リスタがある(例えば特公昭58−23921号公報参
照)、この積層型バリスタ3゜は、ZnOを主成分とす
るセラミクス層31と内部電極32とを交互に積層して
一体焼結するとともに、該焼結体33の左、右端面33
a、33bに外部型8iI34を形成し、上記各内部電
極32の一端面32aを、上記焼結体33の左、右端面
33a、33bに交互に露出させて上記外部電極34に
接続した構成となっている。In general, a varistor is a resistive element whose resistance value changes non-linearly depending on the applied voltage. Conventionally, as such a varistor, there is a rectangular parallelepiped-shaped multilayer varistor as shown in Fig. 6. (For example, see Japanese Patent Publication No. 58-23921.) This multilayer varistor 3° is made by alternately stacking ceramic layers 31 mainly composed of ZnO and internal electrodes 32 and sintering them together. 33 left and right end surfaces 33
a, 33b, and one end surface 32a of each internal electrode 32 is alternately exposed to the left and right end surfaces 33a, 33b of the sintered body 33 and connected to the external electrode 34. It has become.
ところで、上記従来の積層型バリスタ3oは、焼結体3
3として見れば、内部電極32の一端面32aが外部に
露出した構造であるから、湿度の高い雰囲気中において
は上記内部電極32の露出部分が変質し易いという問題
がある。By the way, the conventional multilayer varistor 3o described above has a sintered body 3
3, since the structure is such that one end surface 32a of the internal electrode 32 is exposed to the outside, there is a problem that the exposed portion of the internal electrode 32 is easily deteriorated in a humid atmosphere.
また、この種の積層型バリスタ30を配線用基板に半田
付は接続すると、外部電極34が銀の焼付は電極からな
のものでは半田中に銀が溶融して取り込まれる、いわゆ
る銀くわれが生じていた。In addition, when this type of multilayer varistor 30 is connected to a wiring board by soldering, if the external electrode 34 is baked from the electrode, silver will be melted and incorporated into the solder, resulting in so-called silver cracks. was.
このような銀くわれを防止するため、銀電極の上にニッ
ケル、銅等の耐熱性を有し、半田に溶融しにくい金属層
をめっきにより形成・したり、さらに半田の付着を良好
にすることを目的として、めっきからなる金属層の上に
半田層をめっきにより形成することも行われている。し
かしながら、上記外部電極34の表面にさらに金属層や
半田層を形成すると、めっき液が内部電極の露出部分か
ら侵入し易く、その結果バリスタ特性が劣化するという
問題点がある。In order to prevent such silver corrosion, a heat-resistant metal layer such as nickel or copper that is difficult to melt by solder is formed on the silver electrode by plating, and the solder adhesion is improved. For this purpose, a solder layer is also formed by plating on a metal layer made of plating. However, if a metal layer or a solder layer is further formed on the surface of the external electrode 34, the plating solution tends to enter through the exposed portion of the internal electrode, resulting in a problem that the varistor characteristics deteriorate.
そこで本件出願人は、上記高湿度及びめっき液の侵入に
よる内部電極の変質を防止するために、第5図に示すよ
うな積層型バリスタを提案した(特願昭63−2258
49号)。この積層型バリスタ20は、内部電極21の
一端面21a及び他端面21bを外部に露出しないよう
にセラミクス層24内に埋設させて焼結体22を形成す
るとともに、該焼結体22の両端面22a、22bに、
該焼結体22にAI等を固溶させてなる導出層23を形
成し、該導出層23を介して上記内部電極21の一端面
21aを交互に電気的に導出して構成されている。この
積層型バリスタ20によれば、内部電極21を焼結体2
2内に埋設し、該内部電極21の露出部分をなくしたの
で、湿度の高い雰囲気中やめっき液処理中においても内
部電極21の変質を防止でき、その結果バリスタ特性の
悪化を回避できる。Therefore, in order to prevent deterioration of the internal electrodes due to the above-mentioned high humidity and penetration of plating solution, the applicant proposed a multilayer varistor as shown in FIG.
No. 49). This laminated varistor 20 has one end surface 21a and the other end surface 21b of an internal electrode 21 buried in a ceramic layer 24 so as not to be exposed to the outside to form a sintered body 22, and both end surfaces of the sintered body 22. 22a, 22b,
A lead-out layer 23 made of a solid solution of AI or the like is formed in the sintered body 22, and one end surface 21a of the internal electrode 21 is electrically led out alternately through the lead-out layer 23. According to this multilayer varistor 20, the internal electrode 21 is connected to the sintered body 2.
Since the exposed portion of the internal electrode 21 is eliminated, deterioration of the internal electrode 21 can be prevented even in a humid atmosphere or during plating solution treatment, and as a result, deterioration of varistor characteristics can be avoided.
ところで、上記積層型バリスタ20においては、耐湿性
や耐めっき性は向上できるものの、もれ電流が生じ易く
、場合によっては短絡する恐れがあるということが判明
した。これはバリスタ特性を得るための内部電極21同
土間以外の部分において電流が流れるためであり、例え
ば上記導出層23は、AI等を固溶させるという構造上
、その上。By the way, it has been found that although the above-described multilayer varistor 20 can improve moisture resistance and plating resistance, leakage current is likely to occur, and there is a risk of short circuit in some cases. This is because a current flows in a portion other than the earthen floor of the internal electrode 21 for obtaining varistor characteristics.For example, the derivation layer 23 has a structure in which AI or the like is dissolved therein.
下部23a部分が内方に張り出し易く、そのため最上部
、最下部の内部電極21の他端面21bと上記導出層2
3の上、下部23aとの隙間が小さくなり、この部分に
おいてもれ電流が生じるものと考えられる。The lower part 23a tends to protrude inward, so that the other end surfaces 21b of the uppermost and lowermost internal electrodes 21 and the derivation layer 2
It is thought that the gap between the upper and lower portions 23a of 3 becomes smaller, and leakage current occurs in these parts.
本発明の目的は、高湿度やめっき液による内部電極の変
質を防止してバリスタ特性の悪化を回避でき、さらにも
れ電流を防止して品質の信転性を向上できる積層型バリ
スタを提供することにある。An object of the present invention is to provide a multilayer varistor that can prevent deterioration of varistor characteristics by preventing deterioration of internal electrodes due to high humidity and plating solution, and can further improve reliability of quality by preventing leakage current. There is a particular thing.
そこで本発明は、セラミクス層と内部電極とを、該内部
電極の一端面が接続ギャップを開けて内方に位置し、か
つ他端面が上記接続ギャップより広い非接続ギャップを
開けて内方に位置するように交互に積層して積層体を形
成し、該積層体の両端の接続ギャップ部分を低抵抗化さ
せることにより、上記内部電極の一端面を該積層体の端
面に交互に電気的に導出する導出層を形成し、さらに上
記積層体の雨量外層に位置する内部電極の上記非接続ギ
ャップを他の内部電極の非接続ギャップより大きくした
ことを特徴とする積層型バリスタである。Therefore, the present invention connects a ceramic layer and an internal electrode such that one end surface of the internal electrode is located inward with a connection gap, and the other end surface is located inward with a non-connection gap wider than the connection gap. By alternately stacking the layers to form a laminate, and lowering the resistance of the connection gap portions at both ends of the laminate, one end surface of the internal electrodes is electrically led out alternately to the end surface of the laminate. The multilayer varistor is characterized in that a derivation layer is formed, and the non-connection gap of the internal electrode located in the outer rain layer of the multilayer body is made larger than the non-connection gap of the other internal electrodes.
ここで、上記接続ギャップとは内部電極の一端面から積
層体の端面までの距離の意味であり、非接続ギャップと
は内部電極の他端面から積層体の端面までの距離の意味
である。Here, the connection gap means the distance from one end surface of the internal electrode to the end surface of the laminate, and the non-connection gap means the distance from the other end surface of the internal electrode to the end surface of the laminate.
また、上記雨量外層の内部電極の非接続ギャップを他の
内部電極の接続ギャップより大きくするとは、雨量外層
の内部電極の一端面を導出層に接続し、かつその長さを
他の内部電極の長さより短くするとの意味であり、該長
さは上記積層体の長さの1/2を越えないようにするの
が好ましい。Also, making the non-connection gap of the internal electrode of the rain layer outer layer larger than the connection gap of other internal electrodes means that one end surface of the internal electrode of the rain layer outer layer is connected to the derivation layer, and its length is set to be larger than that of the other internal electrodes. This means that the length is shorter than the length, and it is preferable that the length does not exceed 1/2 of the length of the laminate.
本発明に係る積層型バリスタによれば、内部電極の一端
面2他端面をそれぞれ接続ギャップ、非接続ギャップを
設けて積層体の内方に位置させ、該積層体内に埋設した
ので、上記内部電極の露出部分を完全になくすことがで
き、湿度の高い雰囲気中においても内部電極の変質を防
止できるとともに、外部電極を形成する際のメツキ液の
侵入を阻止でき、その結果バリスタ特性の悪化を回避で
きる。この場合、各内部電極の一端面は導出層に接続さ
れているので、該導出層を介して外部電極に接続できる
。According to the multilayer varistor according to the present invention, one end surface 2 of the internal electrode is located inside the laminate with a connecting gap and a non-connecting gap, respectively, and is embedded in the laminate, so that the internal electrode The exposed part of the varistor can be completely eliminated, preventing deterioration of the internal electrodes even in a humid atmosphere, and preventing the plating liquid from entering when forming the external electrodes, thereby avoiding deterioration of varistor characteristics. can. In this case, since one end surface of each internal electrode is connected to the lead-out layer, it can be connected to the external electrode via the lead-out layer.
また、本発明では、最外層の内部電極の他端面と積層体
の端面との非接続ギャップを他の非接続ギャップより大
きくしたので、上記導出層の上。Furthermore, in the present invention, the non-connection gap between the other end surface of the inner electrode of the outermost layer and the end surface of the laminate is made larger than other non-connection gaps, so that the non-connection gap is larger than the other non-connection gaps.
下部が内方に張り出しても、これと上記他端面との距離
は十分確保されており、その結果この部分に電流が流れ
ることはなく、もれ電流を防止でき、ひいては消費電力
、熱暴走等の問題を解消でき、品質の信鎖性を向上でき
る。Even if the lower part protrudes inward, there is a sufficient distance between it and the other end surface, and as a result, no current flows through this part, preventing leakage current and reducing power consumption, thermal runaway, etc. problems can be resolved and quality reliability can be improved.
以下、本発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図ないし第3図は本発明の一実施例による積層型バ
リスタを説明するための図である。1 to 3 are diagrams for explaining a multilayer varistor according to an embodiment of the present invention.
図において、lは本実施例の積層型バリスタであり、こ
のバリスタ1は直方体状のもので、バリスタ機能を発現
するZnO系セラミクス層2と、ptからなる内部電極
3′、又は3とを交互に積層し、これを一体焼成してな
る焼結体4の左1右端面4a、4bにAg/Paからな
る外部電極5を形成して構成されている。In the figure, l denotes the laminated varistor of this embodiment, and this varistor 1 has a rectangular parallelepiped shape, and a ZnO ceramic layer 2 that exhibits a varistor function and an internal electrode 3' or 3 made of PT are alternately arranged. External electrodes 5 made of Ag/Pa are formed on the left and right end surfaces 4a and 4b of a sintered body 4 formed by laminating them and firing them together.
また、上記内部電極3の一端面3aは互い違いに上記焼
結体4の両端面4a、4bに近接する接続ギャップTを
開けて内方に位Iしており、他端面3bはこれも互い違
いに上記焼結体40両端面4a、4bから上記接続ギャ
ップTより広い非接続ギャップtを開けて内方に位置し
ており、これにより各内部電極3は焼結体4内に埋めこ
まれて封入されている。Further, one end surface 3a of the internal electrode 3 is alternately positioned inwardly with a connecting gap T adjacent to both end surfaces 4a, 4b of the sintered body 4, and the other end surface 3b is also alternately located. A non-connection gap t, which is wider than the connection gap T, is opened from both end surfaces 4a and 4b of the sintered body 40 and is located inwardly, so that each internal electrode 3 is embedded and enclosed within the sintered body 4. has been done.
さらに、上記焼結体4の左、右端面4a、4b部分には
セラミクス層2を低抵抗化してなる導出層6が形成され
ており、該導出層6は上記接続ギヤ711部分より内方
に達し、上記内部電極3の一端面3aに接続される厚さ
になっている。この導出層6は、上記両端面4a、4b
部分にAlを主成分とするペーストを塗布し、これを加
熱することにより焼結体4のZnOに固溶させて、この
部分の抵抗値を減少させることにより形成されたもので
ある。また、上記導出層6の外表面は上記外部電極5に
接続されており、これにより上記各内部電極3は導出層
6を介して電気的に外部電極5に接続されている。Furthermore, a derivation layer 6 made by lowering the resistance of the ceramic layer 2 is formed on the left and right end surfaces 4a and 4b of the sintered body 4, and the derivation layer 6 extends inward from the connection gear 711 portion. The inner electrode 3 has a thickness such that it is connected to one end surface 3a of the internal electrode 3. This derivation layer 6 has the above-mentioned both end surfaces 4a and 4b.
It is formed by applying a paste containing Al as a main component to the portion and heating it to form a solid solution in the ZnO of the sintered body 4, thereby reducing the resistance value of this portion. Further, the outer surface of the derivation layer 6 is connected to the external electrode 5 , so that each of the internal electrodes 3 is electrically connected to the external electrode 5 via the derivation layer 6 .
そして、上記最上部及び最下部の内部1ii3’の他端
面3Cと焼結体4の左、右端面4a、4bとの非接続ギ
ャップ(′は、上記他の内部電極3の非接続ギャップt
より大きく形成されている。The non-connection gap (' is the non-connection gap t of the other internal electrode 3) between the other end surface 3C of the uppermost and lowermost internal electrodes 1ii3' and the left and right end surfaces 4a and 4b of the sintered body 4.
It is formed larger.
即ち、上記最上部及び最下部の内部電極3′の一端面3
aから他端面3Cまでの長さは上記焼結体4の長さlの
172より短く形成されている。That is, one end surface 3 of the uppermost and lowermost internal electrodes 3'
The length from a to the other end surface 3C is shorter than 172, which is the length l of the sintered body 4.
次に本実施例の積層型バリスタlを製造する方法につい
て説明する。Next, a method for manufacturing the multilayer varistor I of this example will be described.
■ まず、Z n O(95,Omoj%)、Coo(
1゜0moj %) 、 MnO(1,0mol
%) 、 S bx 0s(2,0moj!
%) 、 Crl o2 (1,Om
oj! %) を混合してなるセラミクス材料に、B
、O,、SiOx 、PbO,ZnOからなるガラス粉
末をlO−【%加えて原料とし、これに有機バインダー
を混合して、ドクターブレード法によりグリーンシート
を形成する。このグリーンシートを所定の大きさの矩形
状に切断して、多数の矩形状セラミクス層2を形成する
。■ First, Z n O (95, Omoj%), Coo (
1゜0moj%), MnO (1.0mol
%), S bx 0s (2,0moj!
%), Crl o2 (1, Om
oj! %) in a ceramic material made by mixing B
, O,, SiOx, PbO, and ZnO are added as a raw material in 1O-[%, and an organic binder is mixed with this to form a green sheet by a doctor blade method. This green sheet is cut into rectangular shapes of a predetermined size to form a large number of rectangular ceramic layers 2.
■ 次に、第3図に示すように、上記各セラミクスN2
の上面に、ptにビヒクルを混合してなるペーストを印
刷して内部電極3′、3を形成する。この場合、各内部
電極3′、3の一端面3aが、交互にセラミクス層2の
左、右端面2a、2bから接続ギャップTを開けて内側
に位置するようにし、また最上部及び最下部に位置する
内部型8i3゛以外の内部電極3の他端面3bが、交互
にセラミクス層2の左、右端面2a、2bから非接続ギ
ャップ【を開けて内側に位置するようにする。■Next, as shown in Figure 3, each of the above ceramics N2
Internal electrodes 3' and 3 are formed by printing a paste made of a mixture of PT and vehicle on the upper surface of the electrode. In this case, one end surface 3a of each of the internal electrodes 3', 3 is located inward from the left and right end surfaces 2a, 2b of the ceramic layer 2 alternately with connection gaps T opened, and The other end surfaces 3b of the internal electrodes 3 other than the internal molds 8i3' located therein are alternately located inside with non-connection gaps opened from the left and right end surfaces 2a and 2b of the ceramic layer 2.
そして、上記最上部及び最下部に位置する内部電極3′
の他端面3cが、それぞれセラミクス層2の左、右端面
2a、2bから非接続ギャップt′を開けて略中央部に
位置するように形成する。And the internal electrodes 3' located at the top and bottom
The other end surface 3c is formed so as to be located approximately in the center with a non-connection gap t' opened from the left and right end surfaces 2a and 2b of the ceramic layer 2, respectively.
■ 次に、セラミクス層2と内部電極3′又は3とが交
互に重なるように、かつ該内部電極3′3の一端面3a
が交互に左、右に位置するように順次積層し、さらにこ
の積層体の上面にダミーとしてのセラミクスシート8を
重ね、これをプレスで加圧、圧着して積層体を形成する
。するとこれにより、各内部電極3は完全に積層体内に
埋設されて封入されていることとなる。(2) Next, the ceramic layer 2 and the internal electrodes 3' or 3 are alternately overlapped, and the one end surface 3a of the internal electrode 3'3 is
are stacked one after another so that they are alternately located on the left and right sides, and then a dummy ceramic sheet 8 is placed on top of this laminate, and this is pressed and bonded with a press to form a laminate. As a result, each internal electrode 3 is completely embedded and encapsulated within the laminate.
■ そして、上記積層体を空気中にて1200℃×3時
間で加熱焼成し、焼結体4を得る0次に、この焼結体4
の左、右端面4a、4bにAIを主成分とするペースト
を塗布し、これを1000℃×1時間加熱処理する。こ
の熱処理によって、上記焼結体4の両端面4a、4b部
分のZnOにAjl O2が固溶し、上記両端面4a、
4b部分の抵抗値が減少して導出層6が形成され、該導
出層6と各内部電極3の一端面3aとが接続されること
となる。ここで、上記導出層6を形成する金属としてA
1の他にGa、Gd、Y等が採用できる。(2) Then, the above laminate is heated and fired in air at 1200°C for 3 hours to obtain a sintered body 4. Next, this sintered body 4 is obtained.
A paste containing AI as a main component is applied to the left and right end surfaces 4a and 4b of the substrate, and the paste is heat-treated at 1000° C. for 1 hour. Through this heat treatment, AjlO2 is dissolved in ZnO on both end surfaces 4a and 4b of the sintered body 4, and the end surfaces 4a and
The resistance value of the portion 4b decreases to form a derivation layer 6, and the derivation layer 6 and one end surface 3a of each internal electrode 3 are connected. Here, as the metal forming the derivation layer 6, A
In addition to 1, Ga, Gd, Y, etc. can be used.
■ 最後に、上記導出層6の外表面に、Agを主体とし
てPdを添加してなるペーストを塗布し、これを焼き付
けて外部電極5を形成する。これにより、本実施例の積
層型バリスタ1が製造される。(2) Finally, a paste consisting mainly of Ag with addition of Pd is applied to the outer surface of the derivation layer 6, and this is baked to form the external electrode 5. In this way, the multilayer varistor 1 of this example is manufactured.
次に本実施例の作用効果について説明する。Next, the effects of this embodiment will be explained.
本実施例によれば、各内部電極3をセラミクス層2内に
封入し、該内部電極3を露出させないようにしたので、
高湿度の雰囲気中で使用しても、内部電極3が変質する
ことはなく、しかも焼結体4を電解めっき液中に浸漬し
ても該めっき液が侵入することはないから、バリスタ特
性の悪化を防止できる。また、本実施例では、導出層6
と各内部電極3とを電気的に接続し、該導出層6を介し
て外部電極5に接続したので、上記内部電極3を内方に
封入しながら外部に導出できる。しかもこの導出層6は
AN等のペーストを塗布し、加熱するだけで実現でき、
製造が容易である。According to this embodiment, each internal electrode 3 is encapsulated within the ceramic layer 2 so that the internal electrode 3 is not exposed.
Even when used in a high humidity atmosphere, the internal electrodes 3 will not change in quality, and even if the sintered body 4 is immersed in an electrolytic plating solution, the plating solution will not penetrate, so the varistor characteristics can be improved. Deterioration can be prevented. Furthermore, in this embodiment, the derivation layer 6
and each internal electrode 3 are electrically connected and connected to the external electrode 5 via the derivation layer 6, so that the internal electrode 3 can be led out to the outside while being sealed inside. Moreover, this derivation layer 6 can be realized by simply applying a paste such as AN and heating it.
Easy to manufacture.
また、本実施例によれば、最上部、最下部の内部電極3
゛の他端面3Cと焼結体4の両端面4a。Further, according to this embodiment, the uppermost and lowermost internal electrodes 3
``Other end surface 3C and both end surfaces 4a of the sintered body 4.
4bとの非接続ギャップt′を他の内部電極3の非接続
ギャップtより大きくしたので、つまり上記他端面3C
と導出層6及び外部電極5との距離が十分層されている
から、バリスタ特性を得るための内部電極3同土間以外
の部分に電流が流れることはなく、その結果もれ電流を
防止でき、ひいては消費電力、熱暴走等の問題を解消で
き、品質の信頼性を向上できる。4b is made larger than the non-connection gap t of the other internal electrodes 3, that is, the other end surface 3C
Since the distance between the derivation layer 6 and the external electrode 5 is sufficient, current will not flow to any part other than the earthen floor of the internal electrode 3 for obtaining varistor characteristics, and as a result, leakage current can be prevented. Furthermore, problems such as power consumption and thermal runaway can be resolved, and quality reliability can be improved.
表は、本実施例の効果を確認するために行った特性試験
の結果を示す。The table shows the results of characteristic tests conducted to confirm the effects of this example.
この試験では、本実施例の製造方法により作成した積層
型バリスタを、温度60℃、相対湿度90%の雰囲気中
に1000時間放置し、しかる後V、、、及び■。1□
の変化率を調べた。また、もれ電流μAはVlaAの6
0%の電圧で測定した。なお、比較のため、内部電極の
端面を焼結体の表面に露出させてなる従来の積層型バリ
スタ(第6図の構造のもの)、及び内部電極を焼結体内
に埋設し、全ての内部電極の長さを同一にしてなる比較
のための積層型バリスタ(第5図の構造のもの)につい
ても同様の試験を行った。In this test, the laminated varistor produced by the manufacturing method of this example was left in an atmosphere with a temperature of 60° C. and a relative humidity of 90% for 1000 hours, and then V, , and ■. 1□
The rate of change was investigated. Also, the leakage current μA is 6 of VlaA.
Measured at 0% voltage. For comparison, a conventional multilayer varistor (with the structure shown in Fig. 6) in which the end faces of the internal electrodes are exposed on the surface of the sintered body, and a conventional multilayer varistor in which the internal electrodes are buried in the sintered body and all internal A similar test was also conducted on a comparative multilayer varistor (having the structure shown in FIG. 5) having electrodes of the same length.
表からも明らかなように、内部電極の端面が露出してい
る従来試料(第2欄)の場合は、もれ電流はそれほど大
きくないものの、耐湿性を示すVlaA r Va、t
am (7)変化率は−8,−23%となッテおり、バ
リスタ特性が劣化している。また、内部電極を焼結体内
に埋設してなる比較試料(第3欄)の場合は、VlaA
+ Vo、+*a (7)変化率は−4゜6%であ
り、上記従来試料に比べて耐湿性が改善されていること
がわかる。しかし、もれ電流は0.95μAと大きくな
っている。これに対して、本実施例試料(第1欄)では
、VIIIIA + vl+aA (D変化率は−4
,−6%となっており、上記比較試料と同様に耐湿性が
向上しており、しかももれ電流においても0.13μA
と小さくなっており、従来試料、比較試料より改善され
ていることがわかる。As is clear from the table, in the case of the conventional sample (column 2) in which the end face of the internal electrode is exposed, the leakage current is not so large, but the VlaA r Va,t exhibits moisture resistance.
am (7) The rate of change is -8%, -23%, and the varistor characteristics are deteriorated. In addition, in the case of the comparative sample (column 3) in which the internal electrode is embedded in the sintered body, VlaA
+Vo, +*a (7) The rate of change was -4°6%, indicating that the moisture resistance was improved compared to the conventional sample. However, the leakage current is as large as 0.95 μA. On the other hand, in the sample of this example (column 1), VIIIA + vl + aA (D change rate is -4
, -6%, the moisture resistance is improved like the above comparative sample, and the leakage current is also 0.13 μA.
It can be seen that this is an improvement over the conventional sample and comparative sample.
また、本実施例試料の外部電極にめっき処理により金属
層を施したが、これによる特性の劣化は全く認められな
かった。Furthermore, although a metal layer was applied to the external electrode of the sample of this example by plating, no deterioration of the characteristics was observed at all due to this.
第4図は上記実施例の変形例を示し、図中、第1図と同
一符号は同−又は相当部分を示す。FIG. 4 shows a modification of the above embodiment, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts.
この積層型バリスタlは、最上部及び最下部の内部電極
9の左、右外端面9aを導出層6に接続し、これの内端
面9b同士の間に隙間を設けて上記内部電極9を2分割
し、これにより該内端面9bと対向する側の焼結体4の
左、右端面4a、4bとの間に他の非接続ギャップ【に
より大きい非接続ギャップt′を形成した例である。こ
の場合においても、内部電極の変質を防止できるととも
に、もれ電流を防止でき上記実施例と同様の効果が得ら
れる。また、この構造によれば、内部電極の印刷及び積
層作業を容易化できる。This multilayer varistor l connects the left and right outer end surfaces 9a of the uppermost and lowermost internal electrodes 9 to the lead-out layer 6, and provides a gap between the inner end surfaces 9b of the inner electrodes 9 to connect the internal electrodes 9 to the two. This is an example in which a larger non-connection gap t' is formed between the inner end surface 9b and the left and right end surfaces 4a and 4b of the sintered body 4 on the opposite side. In this case as well, deterioration of the internal electrodes can be prevented and leakage current can be prevented, and the same effects as in the above embodiment can be obtained. Moreover, according to this structure, printing and lamination work of internal electrodes can be facilitated.
以上のように、本発明に係る積層型バリスタによれば、
内部電極の一端面を接続ギャップを開けて内方に位置さ
せ、他端面を接続ギャップより広い非接続ギャップを開
けて内方に位置させ、積層体の両端部分に上記内部電極
の一端面を交互に電気的に導出する導出層を形成すると
ともに、上記最上部及び最下部の内部電極の上記非接続
ギャップを他の内部電極の非接続ギャップより大きくし
たので、高湿度やめっき液の侵入による内部電極の変質
を防止でき、バリスタ特性の悪化を回避できる効果があ
るとともに、もれ電流を防止して品質の信鯨性を向上で
きる効果がある。As described above, according to the multilayer varistor according to the present invention,
One end surface of the internal electrode is positioned inward with a connection gap, the other end surface is positioned inward with a non-connection gap wider than the connection gap, and one end surface of the internal electrode is alternately placed on both ends of the laminate. In addition to forming a lead-out layer that electrically leads to This has the effect of preventing electrode deterioration and deterioration of varistor characteristics, as well as preventing leakage current and improving quality reliability.
第1図ないし第3図は本発明の一実施例による積層型バ
リスタを説明するための図であり、第1図は第2図のI
−1線断面図、第2図はその斜視図、第3図はその分解
した状態の平面図、第4図は上記実施例の変形例を示す
断面図、第5図は本発明の成立過程を説明するための積
層型バリスタの断面図、第6図は従来の積層型バリスタ
を示す断面図である。
図において、1は積層型バリスタ、2はセラミクス層、
3は他の内部電極、3′、9は最上部。
最下部(最外層)の内部電極、3a、9aは内部電極の
一端面、3bは他端面、3c、9bは最上部及び最下部
の内部電極の他端面、4は焼結体(積層体)、4a、4
bは焼結体の左、右端面、6は導出層、Tは接続ギャッ
プ、tは非接続ギャップ、t′は最上部及び最下部の内
部電極の非接続ギャップである。1 to 3 are diagrams for explaining a multilayer varistor according to an embodiment of the present invention, and FIG. 1 is a diagram showing the I of FIG.
-1 line sectional view, FIG. 2 is a perspective view thereof, FIG. 3 is a plan view of the exploded state, FIG. 4 is a sectional view showing a modification of the above embodiment, and FIG. 5 is a process of establishing the present invention. FIG. 6 is a sectional view showing a conventional multilayer varistor. In the figure, 1 is a multilayer varistor, 2 is a ceramic layer,
3 is another internal electrode, 3' and 9 are the topmost electrodes. The lowermost (outermost layer) internal electrode, 3a and 9a are one end surface of the internal electrode, 3b is the other end surface, 3c and 9b are the other end surfaces of the uppermost and lowermost internal electrodes, 4 is a sintered body (laminated body) , 4a, 4
b is the left and right end surfaces of the sintered body, 6 is a lead-out layer, T is a connection gap, t is a non-connection gap, and t' is a non-connection gap between the uppermost and lowermost internal electrodes.
Claims (1)
とを、該内部電極の一端面がセラミクス層の端面から接
続ギャップを開けて内方に位置し、他端面が上記接続ギ
ャップより広い非接続ギャップを開けて内方に位置する
ように交互に積層して積層体を形成し、該積層体の両端
の接続ギャップ部分を低抵抗化させることにより、該積
層体の両端面に上記内部電極の一端面を交互に電気的に
導出する導出層を形成し、さらに上記積層体の両最外層
に位置する内部電極の上記非接続ギャップを他の内部電
極の非接続ギャップより大きくしたことを特徴とする積
層型バリスタ。(1) A ceramic layer that exhibits a varistor function and an internal electrode are arranged such that one end surface of the internal electrode is located inward from the end surface of the ceramic layer with a connection gap, and the other end surface is a non-connection gap that is wider than the connection gap. By forming a laminate by alternately stacking the inner electrodes so that they are open and positioned inward, and by lowering the resistance of the connection gap portions at both ends of the laminate, one of the internal electrodes is formed on both end surfaces of the laminate. It is characterized by forming lead-out layers that electrically lead out the end faces alternately, and further making the non-connection gaps of the internal electrodes located at both outermost layers of the laminate larger than the non-connection gaps of the other internal electrodes. Laminated varistor.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1082636A JPH02260604A (en) | 1989-03-31 | 1989-03-31 | Lamination type varistor |
| US07/404,838 US5075665A (en) | 1988-09-08 | 1989-09-08 | Laminated varistor |
| DE3930000A DE3930000A1 (en) | 1988-09-08 | 1989-09-08 | VARISTOR IN LAYER DESIGN |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1082636A JPH02260604A (en) | 1989-03-31 | 1989-03-31 | Lamination type varistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02260604A true JPH02260604A (en) | 1990-10-23 |
Family
ID=13779919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1082636A Pending JPH02260604A (en) | 1988-09-08 | 1989-03-31 | Lamination type varistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02260604A (en) |
-
1989
- 1989-03-31 JP JP1082636A patent/JPH02260604A/en active Pending
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