JPH02302005A - Laminate-type varistor - Google Patents

Laminate-type varistor

Info

Publication number
JPH02302005A
JPH02302005A JP1123780A JP12378089A JPH02302005A JP H02302005 A JPH02302005 A JP H02302005A JP 1123780 A JP1123780 A JP 1123780A JP 12378089 A JP12378089 A JP 12378089A JP H02302005 A JPH02302005 A JP H02302005A
Authority
JP
Japan
Prior art keywords
internal electrodes
sintered body
laminate
varistor
resistance layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1123780A
Other languages
Japanese (ja)
Inventor
Hiroaki Taira
浩明 平
Kazuyoshi Nakamura
和敬 中村
Yasunobu Yoneda
康信 米田
Yukio Sakabe
行雄 坂部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP1123780A priority Critical patent/JPH02302005A/en
Priority to US07/404,838 priority patent/US5075665A/en
Priority to DE3930000A priority patent/DE3930000A1/en
Publication of JPH02302005A publication Critical patent/JPH02302005A/en
Pending legal-status Critical Current

Links

Landscapes

  • Thermistors And Varistors (AREA)

Abstract

PURPOSE:To prevent a quality of internal electrodes from being changed by a method wherein the internal electrodes are buried completely inside a ceramic layer, the left end face and the right end face of a laminated body are coated with a mixture of metal zinc and zinc oxide, this mixture is oxidized and heat-treated and low-resistance layers from which the internal electrodes are extracted alternately are formed. CONSTITUTION:Individual internal electrodes 3 are buried inside a ceramic layer 2. The internal electrodes 3 are not exposed at peripheral edges of a sintered body 4. As a result, even when the internal electrodes 3 are used in a high-humidity atmosphere, their quality is not changed. Even when the sintered body 4 is immersed in an electrolytic plating liquid, the plating liquid does not creep. As a result, it is possible to prevent a varistor characteristic from being aggravated and to enhance quality. In addition, since low-resistance layers 6 are formed on the left end face and the right end face 4a, 4b of the sintered body 4, the resistance layers 6 are connected to end faces 3a of the internal electrodes 3; the internal electrodes 3 can be connected to external electrodes 5 via the resistance layers 6; the internal electrodes 3 can be extracted even in a state that they have been sealed. The low-resistance layers 6 can be realized when a paste composed of metal zinc and zinc oxide is coated and this paste is heat-treated simultaneously with a baking operation of a laminated body.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電圧非直線性抵抗として機能する積層型バリ
スタに関し、特に内部電極の変質を防止してバリスタ特
性の悪化を回避でき、部品の信鯨性を向上できるように
した構造に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multilayer varistor that functions as a voltage non-linear resistor, and in particular can prevent deterioration of varistor characteristics by preventing deterioration of internal electrodes, and improves the performance of components. It relates to a structure that improves credibility.

〔従来の技術〕[Conventional technology]

一般に、バリスタは、印加電圧に応じて抵抗値が非直線
的に変化する抵抗体素子であり、このようなバリスタと
して、従来、第6図に示すような直方体状の積層型バリ
スタがある(例えば特公昭5B−23921号公報参照
)、この積層型バリスタ10は、ZnOを主成分とする
セラミクス層11と内部型8i112とを交互に積層し
て一体焼結するとともに、該焼結体13の左1右端面1
3a、13bに外部電極14を形成して構成されている
。また、上記各内部電極12の一端面12aは、上記焼
結体13の左、右端面13a、13bに交互に露出され
て上記外部電極14に接続されている。
Generally, a varistor is a resistive element whose resistance value changes non-linearly depending on the applied voltage. Conventionally, as such a varistor, there is a rectangular parallelepiped-shaped multilayer varistor as shown in FIG. (Refer to Japanese Patent Publication No. 5B-23921), this multilayer varistor 10 is made by alternately stacking and integrally sintering ceramic layers 11 mainly composed of ZnO and internal molds 8i112, and 1 Right end surface 1
External electrodes 14 are formed on 3a and 13b. Further, one end surface 12a of each of the internal electrodes 12 is alternately exposed to left and right end surfaces 13a and 13b of the sintered body 13 and connected to the external electrode 14.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、上記従来の積層型バリスタ10は、焼結体1
3として見れば、内部電極12の一端面12aが外部に
露出した構造であるから、湿度の高い雰囲気中において
は上記内部電極12の露出部分が変質し易く、まためっ
き処理により上記外部を極14を形成する際に、めっき
液が内部電極12の露出部分から侵入し易く、その結果
バリスタ特性が悪化し、品質に対する信頼性に劣るとい
う問題点がある。
By the way, the conventional multilayer varistor 10 described above has a sintered body 1
3, since the structure is such that one end surface 12a of the internal electrode 12 is exposed to the outside, the exposed portion of the internal electrode 12 is likely to deteriorate in a high humidity atmosphere, and the external part 12a is easily damaged by plating. When forming the internal electrodes 12, the plating solution tends to enter through the exposed portions of the internal electrodes 12, resulting in deterioration of the varistor characteristics and poor quality reliability.

ここで、上記高湿度やめっき液の侵入による内部電極1
2の変質を防止するには、該内部電極ヱ2の一端TjM
 12 aをセラミクス層ll内に封入して外部に露出
させないようにすることが考えられる。しかしこのよう
にすると内部電極12を外部電8i14に接続できない
ことから、このままでは採用できない。
Here, internal electrode 1 due to the above-mentioned high humidity and invasion of plating solution.
In order to prevent deterioration of the internal electrode 2, one end TjM of the internal electrode 2 must be
It is conceivable to encapsulate 12a in the ceramic layer 11 so as not to expose it to the outside. However, if this is done, the internal electrode 12 cannot be connected to the external electrode 8i14, so it cannot be adopted as is.

本発明は上記従来の問題点を解決するためになされたも
ので、高湿度やめりき液の侵入による内部電極の変質を
防止してバリスタ特性の悪化を回避でき、ひいては品質
への信頼性を向上できる積層型バリスタを提供すること
を目的としている。
The present invention has been made to solve the above-mentioned conventional problems, and can prevent deterioration of varistor characteristics by preventing deterioration of internal electrodes due to high humidity and intrusion of plating fluid, thereby improving quality reliability. The aim is to provide a multilayer varistor that can.

〔問題点を解決するための手段〕 そこで本発明は、セラミクス層と内部電極とを交互に積
層して積層体を形成してなる積層型バリスタにおいて、
上記内部電極を上記積層体の周縁に露出しないようセラ
ミクス層の内側に埋設するとともに、該積層体の両端面
部分に、金属亜鉛と酸化亜鉛との混合物を塗布し、これ
を酸化熱処理することにより、上記内部電極を交互に導
出する低抵抗層を形成したことを特徴としている。
[Means for Solving the Problems] Therefore, the present invention provides a multilayer varistor in which ceramic layers and internal electrodes are alternately stacked to form a multilayer body.
By burying the internal electrodes inside the ceramic layer so as not to expose them to the periphery of the laminate, and applying a mixture of metallic zinc and zinc oxide to both end surfaces of the laminate and subjecting it to oxidation heat treatment. , a low resistance layer is formed from which the internal electrodes are alternately led out.

ここで、上記低抵抗層は、金属亜鉛と酸化亜鉛とを混合
してなる粉末をペースト状に形成し、これを積層体の両
端面に塗布し、しかる後空気中にて焼成することにより
、上記積層体の両端面部分に酸素欠陥の多い低抵抗セラ
ミクス層を形成することにより実現できる。
Here, the low resistance layer is formed by forming a powder made of a mixture of metal zinc and zinc oxide into a paste form, applying this to both end faces of the laminate, and then baking it in air. This can be achieved by forming low-resistance ceramic layers with many oxygen defects on both end faces of the laminate.

〔作用〕[Effect]

本発明に係る積層型バリスタによれば、内部電極をセラ
ミクス層内に埋設し、該内部電極の露出部分を完全にな
くしたので、温度の高い雰囲気中においても内部電極の
変質を防止できるとともに、外部電極を形成する際のめ
っき液の侵入を阻止でき、その結果バリスタ特性の悪化
を回避で、品質への信頼性を向上できる。
According to the multilayer varistor according to the present invention, the internal electrodes are buried in the ceramic layer and the exposed parts of the internal electrodes are completely eliminated, so that deterioration of the internal electrodes can be prevented even in a high temperature atmosphere, and It is possible to prevent the plating solution from entering when forming the external electrodes, thereby avoiding deterioration of varistor characteristics and improving quality reliability.

また、本発明では、内部電極は積層体の両端面部分に形
成された低抵抗層に接続されているので、該低抵抗層の
外表面に外部電極を形成することにより、上記内部電極
を外部に導出できる。
Furthermore, in the present invention, since the internal electrodes are connected to the low resistance layers formed on both end surfaces of the laminate, by forming the external electrodes on the outer surfaces of the low resistance layers, the internal electrodes can be connected to the external electrodes. It can be derived as follows.

さらに、上記低抵抗層は、積層体の場面部分に金属亜鉛
と酸化亜鉛との混合ペーストを塗布し、これを空気中に
て加熱焼成するだけで実現でき、製造が容易である。
Furthermore, the low resistance layer can be easily manufactured by simply applying a mixed paste of metal zinc and zinc oxide to the surface area of the laminate and heating and baking it in air.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図ないし第3図は本発明の一実施例による積層型バ
リスタを説明するための図である。
1 to 3 are diagrams for explaining a multilayer varistor according to an embodiment of the present invention.

図において、1は本実施例の積層型バリスタであり、こ
のバリスタ1は直方体状のもので、ZnOを主成分とす
るセラミクス層2と、ptからなる内部電極3とを交互
に積層し、これを一体焼成してなる焼結体4の左、右端
面4a、4bにAg/Pdからなる外部を極5を形成し
て構成されている。また、上記各内部電極3の周縁はセ
ラミクス層2の内側に位置しており、つまり内部電極3
は焼結体4内に埋め込まれて封入されている。この場合
、上記各内部電極3の一端面3aは互い違いに上記焼結
体4の左1右端面4a、4bに近接して位置しており、
他端面3bは焼結体4の左。
In the figure, reference numeral 1 denotes the multilayer varistor of this embodiment. This varistor 1 has a rectangular parallelepiped shape, and has ceramic layers 2 mainly composed of ZnO and internal electrodes 3 made of PT laminated alternately. External poles 5 made of Ag/Pd are formed on the left and right end faces 4a, 4b of a sintered body 4 formed by integrally firing the above. Further, the periphery of each internal electrode 3 is located inside the ceramic layer 2, that is, the internal electrode 3 is located inside the ceramic layer 2.
is embedded and enclosed within the sintered body 4. In this case, one end surface 3a of each of the internal electrodes 3 is alternately located close to the left and right end surfaces 4a and 4b of the sintered body 4,
The other end surface 3b is on the left side of the sintered body 4.

右端面4a、4bから少し離れて位置している。It is located a little apart from the right end faces 4a and 4b.

そして、上記焼結体4の左、右端面4a、4b部分には
低抵抗層6が形成されており、該低抵抗層6は上記各内
部電極3の一端面3aに達する厚さになっている。この
低抵抗層6は、金属亜鉛と酸化亜鉛とを混合してなるペ
ーストを上記焼結体4の左、右端面4a、4bに塗布し
、これを空気中にて加熱処理することにより形成された
ものである。また、上記低抵抗層6の外表面は外部電極
5に接続されており、これにより上記内部電極3は低抵
抗層6を介して外部電極5に接続されている。
A low resistance layer 6 is formed on the left and right end surfaces 4a and 4b of the sintered body 4, and the low resistance layer 6 has a thickness that reaches one end surface 3a of each internal electrode 3. There is. This low resistance layer 6 is formed by applying a paste made of a mixture of metallic zinc and zinc oxide to the left and right end surfaces 4a and 4b of the sintered body 4, and heat-treating it in air. It is something that Further, the outer surface of the low resistance layer 6 is connected to the external electrode 5, and thereby the internal electrode 3 is connected to the external electrode 5 via the low resistance layer 6.

次に本実施例の積層型バリスタ1の製造方法について説
明する。
Next, a method for manufacturing the multilayer varistor 1 of this embodiment will be described.

■ まず、Z n O(95,0moi%)、Co0(
1゜0Ilo1%)+ M n O(1,Omoj!%
)、S bz O* (2,0−01%L Cr t 
O3(1−01101%)を混合してなるセラミクス材
料に、Bz Os 、S fox 、PbO。
■ First, Z n O (95.0 moi%), Co0 (
1゜0Ilo1%)+M n O(1, Omoj!%
), S bz O* (2,0-01%L Cr t
Bz Os , S fox , and PbO are added to the ceramic material made by mixing O3 (1-01101%).

ZnOからなるガラス粉末を10wt%加えて原料とし
、これに有機バインダーを混合して、ドクターブレード
法によりグリーンシートを形成する0次に、第3図に示
すように、上記グリーンシートを矩形状に切断して、多
数のセラミクス層2を形成する。
Add 10 wt% of glass powder consisting of ZnO as a raw material, mix it with an organic binder, and form a green sheet by the doctor blade method.Next, as shown in Figure 3, the green sheet is shaped into a rectangular shape. A large number of ceramic layers 2 are formed by cutting.

■ 上記各セラミクス層2の上面に、ptにビしクルを
混合してなるペーストを印刷して内部電極3を形成する
。この場合、該内部電極3の各端面がセラミクス層2の
内側に位置するように、かつ上記内部電極3の一端面3
aがセラミクス層2の端面に近接し、他端面3bが少し
離れるように形成する。
(2) On the upper surface of each ceramic layer 2, a paste made of a mixture of PT and vehicle is printed to form internal electrodes 3. In this case, each end surface of the internal electrode 3 is located inside the ceramic layer 2, and one end surface 3 of the internal electrode 3 is
A is formed so that the end face 3b is close to the end face of the ceramic layer 2, and the other end face 3b is a little apart.

■ そして各セラミクス層2を、内部電極3とセラミク
ス層2とが交互に重なるように、かつ内部電極3の一端
面3aが交互に位置するように順次積層し、さらにこの
積層体の上、下面にダミーとしてのセラミクス層7を重
ね、これをプレスで加圧、圧着して積層体を形成する。
(2) Then, the ceramic layers 2 are laminated in sequence so that the internal electrodes 3 and the ceramic layers 2 are alternately overlapped, and the one end surfaces 3a of the internal electrodes 3 are alternately located, and then the upper and lower surfaces of this laminate are stacked. A ceramic layer 7 as a dummy is layered on top of the dummy ceramic layer 7, and this is pressed and bonded with a press to form a laminate.

するとこれにより、各内部電極3は完全に積層体内に埋
設されて封入されることになる。
As a result, each internal electrode 3 is completely embedded and encapsulated within the laminate.

■ 次に金属亜鉛と酸化亜鉛とを1:4の割合で含む混
合粉末にビヒクルを添加してペーストを作成する。そし
て、このペーストを上記積層体の左、右端面、即ち上記
内部電極3の一端面3aと対向する側面に、厚さ50μ
mになるように塗布する。
(2) Next, a vehicle is added to a mixed powder containing zinc metal and zinc oxide in a ratio of 1:4 to create a paste. Then, apply this paste to the left and right end surfaces of the laminate, that is, the side surfaces facing one end surface 3a of the internal electrode 3, to a thickness of 50 μm.
Apply so that it becomes m.

■ 上記積層体を空気中にて1200℃で加熱焼成し、
焼結体4を得る。すると、この熱処理によって、この焼
結体4の左、右端面4a、4b部分に、ZnとZnO,
さらに空気中の08の反応により酸素欠陥状態の低抵抗
層6が形成され、該低抵抗層6と上記内部型8i3の一
端面3aとが接続されることとなる。
■ Heat and bake the above laminate in air at 1200°C,
A sintered body 4 is obtained. Then, by this heat treatment, Zn, ZnO,
Further, due to the reaction of 08 in the air, a low resistance layer 6 in an oxygen-deficient state is formed, and the low resistance layer 6 is connected to one end surface 3a of the internal mold 8i3.

■ 最後に、上記焼結体4の左、右端面4a。■Finally, the left and right end surfaces 4a of the sintered body 4.

4bを除く外表面にマスクを被覆形成し、この状態で電
解めっき処理を施して上記低抵抗層6の外表面に外部電
極5を形成する。なお、上記外部電極5は、上記焼結体
4にAgを主体としてPdを添加してなるペーストを塗
布した後、焼き付けて形成してもよい。これにより、本
実施例の積層型バリスタ1が製造される。
A mask is formed to cover the outer surface except for 4b, and in this state electrolytic plating treatment is performed to form the external electrode 5 on the outer surface of the low resistance layer 6. The external electrode 5 may be formed by applying a paste mainly composed of Ag and adding Pd to the sintered body 4 and then baking the paste. In this way, the multilayer varistor 1 of this example is manufactured.

次に本実施例の作用効果について説明する。Next, the effects of this embodiment will be explained.

本実施例の積層型バリスタ1によれば、各内部電極3を
セラミクス層2内に埋設し、該内部電極3を焼結体4の
周縁に露出させないようにしたので、高湿度の雰囲気中
で使用しても内部電極3が変質することはなく、しかも
焼結体4を電解めっき液中に浸漬しても該めっき液が侵
入することはないから、バリスタ特性の悪化を防止でき
、品質を向上できる。
According to the multilayer varistor 1 of this embodiment, each internal electrode 3 is buried in the ceramic layer 2 so that the internal electrode 3 is not exposed to the periphery of the sintered body 4, so that it can be used in a high humidity atmosphere. The internal electrodes 3 will not change in quality even after use, and even if the sintered body 4 is immersed in an electrolytic plating solution, the plating solution will not enter, so deterioration of varistor characteristics can be prevented and quality can be improved. You can improve.

また、本実施例では、焼結体4の左。右端面4a、4b
部分に低抵抗層6を形成したので、該抵抗層6が上記内
部電極3の一端面3aに接続され、該抵抗層6を介して
内部電極3と外部電極5とを接続でき、内部電極3を封
入した状態でも外部に導出できる。しかもこの低抵抗層
6は金属亜鉛と酸化亜鉛とからなるペーストを塗布し、
上記積層体の焼成と同時に加熱処理するだけで実現でき
るから、製造が容易であるとともに、はとんどコストを
上昇させることはない。
Also, in this embodiment, the left side of the sintered body 4. Right end surface 4a, 4b
Since the low resistance layer 6 is formed in the portion, the resistance layer 6 is connected to one end surface 3a of the internal electrode 3, and the internal electrode 3 and the external electrode 5 can be connected via the resistance layer 6. It can be taken out to the outside even when it is sealed. Moreover, this low resistance layer 6 is coated with a paste consisting of metallic zinc and zinc oxide,
Since this can be achieved by simply performing a heat treatment at the same time as the firing of the laminate, manufacturing is easy and the cost does not increase at all.

第4図及び第5図は本実施例の効果を確認するために行
った耐湿試験の結果を示す特性図である。
FIGS. 4 and 5 are characteristic diagrams showing the results of a moisture resistance test conducted to confirm the effects of this example.

この試験では、本実施例の製造方法により作成した積層
型バリスタを、温度60℃、相対湿度90%の雰囲気中
に1000時間放置した後、VIIIA及びVo。
In this test, the laminated varistors produced by the manufacturing method of this example were left in an atmosphere with a temperature of 60°C and a relative humidity of 90% for 1000 hours, and then VIIIA and Vo.

1oの変化率を調べた。なお、比較のため、内部電極の
端面を焼結体の左、右端面に露出させてなる従来の積層
型バリスタについても同様の試験を行った。
The rate of change of 1o was investigated. For comparison, a similar test was also conducted on a conventional multilayer varistor in which the end faces of the internal electrodes were exposed on the left and right end faces of the sintered body.

第4図はvll、の変化率と経過時間との関係を示し、
第5図はVo、+maの変化率と経過時間との関係を示
す0図中、曲線A(実線)は本実施例試料、曲JIB 
(破線)は従来試料を示す。
Figure 4 shows the relationship between the rate of change of vll and elapsed time,
Figure 5 shows the relationship between the rate of change of Vo and +ma and the elapsed time. In Figure 5, curve A (solid line) is the sample of this example, and the curve JIB.
(Dashed line) indicates the conventional sample.

同図からも明らかなように、Vl+sAの変化率では両
者(曲線A、B)ともそれほど大きな差はないものの、
■。、+aAの変化率では、従来試料Bは一25%変化
しているのに対して、本実施例試料Aは一9%の変化に
改善されており、耐湿性が向上していることがわかる。
As is clear from the figure, although there is not much difference in the rate of change of Vl+sA between the two (curves A and B),
■. , +aA, the conventional sample B has a change of -25%, while the sample A of this example has an improved change of -19%, which shows that the moisture resistance has improved. .

また、本実施例試料に外部電極を形成するためのめっき
処理を施したが、これによる特性の劣化は全く認められ
ず、めっき液の侵入が防止されていることがわかった。
Further, although the sample of this example was subjected to plating treatment to form external electrodes, no deterioration of characteristics due to this was observed at all, and it was found that intrusion of plating solution was prevented.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明に係る積層型バリスタによれば、内
部電極をセラミクス層内に完全に埋設させるとともに、
積層体の左、右端面に金属亜鉛と酸化亜鉛との混合物を
塗布し、これを酸化熱処理することにより、上記内部電
極を交互に導出する低抵抗層を形成したので、高湿度や
めっき液の侵入による内部電極の変質を防止でき、バリ
スタ特性の悪化を回避でき、ひいては品質への信頼性を
向上できる効果がある。
As described above, according to the multilayer varistor of the present invention, the internal electrodes are completely buried in the ceramic layer, and
By applying a mixture of metallic zinc and zinc oxide to the left and right end surfaces of the laminate and subjecting it to an oxidation heat treatment, a low resistance layer from which the internal electrodes are alternately led out was formed, so that it could withstand high humidity and plating solution. This has the effect of preventing deterioration of the internal electrodes due to intrusion, avoiding deterioration of varistor characteristics, and improving reliability of quality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本発明の一実施例による積層型バ
リスタを説明するための図であり、第1図はその断面図
、第2図はその斜視図、第3図はその分解斜視図、第4
図及び第5図はそれぞれ本実施例の効果を示す特性図、
第6図は従来の積層型バリスタを示す断面図である。 図において、1は積層型バリスタ、2はセラミクス層、
3は内部電極、3aは内部電極の一端、4は焼結体(積
層体)、6は低抵抗層である。 特許出願人    株式会社 村田製作所代理人 弁理
士    下車  努 第1図 第2図 第3図 第4図 比重時間(h) 絃過吟間(h) 第6図 ゛10
1 to 3 are diagrams for explaining a multilayer varistor according to an embodiment of the present invention, in which FIG. 1 is a sectional view thereof, FIG. 2 is a perspective view thereof, and FIG. 3 is an exploded perspective view thereof. Figure, 4th
5 and 5 are characteristic diagrams showing the effects of this embodiment, respectively.
FIG. 6 is a sectional view showing a conventional multilayer varistor. In the figure, 1 is a multilayer varistor, 2 is a ceramic layer,
3 is an internal electrode, 3a is one end of the internal electrode, 4 is a sintered body (laminate), and 6 is a low resistance layer. Patent Applicant Murata Manufacturing Co., Ltd. Agent Patent Attorney Tsutomu Figure 1 Figure 2 Figure 3 Figure 4 Specific Gravity Time (h) Gravity Time (h) Figure 6゛10

Claims (1)

【特許請求の範囲】[Claims] (1)バリスタ機能を発現するセラミクス層と内部電極
とを交互に積層して積層体を形成し、各内部電極の一端
を該積層体の端面に導出してなり、電圧非直線性抵抗と
して機能する積層型バリスタにおいて、上記内部電極を
上記積層体の周縁に露出しないようセラミクス層の内側
に埋設するとともに、該積層体の両端部分に、金属亜鉛
と酸化亜鉛との混合物を付加し、これを酸化熱処理する
ことにより低抵抗層を形成し、該低抵抗層により上記内
部電極の一端を交互に上記積層体の端面に導出したこと
を特徴とする積層型バリスタ。
(1) A laminate is formed by alternately laminating ceramic layers that exhibit a varistor function and internal electrodes, and one end of each internal electrode is led out to the end surface of the laminate, which functions as a voltage nonlinear resistor. In the multilayer varistor, the internal electrodes are buried inside the ceramic layer so as not to be exposed to the periphery of the multilayer body, and a mixture of metallic zinc and zinc oxide is added to both ends of the multilayer body. A multilayer varistor, characterized in that a low resistance layer is formed by oxidation heat treatment, and one end of the internal electrode is alternately guided to an end surface of the multilayer body by the low resistance layer.
JP1123780A 1988-09-08 1989-05-16 Laminate-type varistor Pending JPH02302005A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1123780A JPH02302005A (en) 1989-05-16 1989-05-16 Laminate-type varistor
US07/404,838 US5075665A (en) 1988-09-08 1989-09-08 Laminated varistor
DE3930000A DE3930000A1 (en) 1988-09-08 1989-09-08 VARISTOR IN LAYER DESIGN

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1123780A JPH02302005A (en) 1989-05-16 1989-05-16 Laminate-type varistor

Publications (1)

Publication Number Publication Date
JPH02302005A true JPH02302005A (en) 1990-12-14

Family

ID=14869106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1123780A Pending JPH02302005A (en) 1988-09-08 1989-05-16 Laminate-type varistor

Country Status (1)

Country Link
JP (1) JPH02302005A (en)

Similar Documents

Publication Publication Date Title
US5075665A (en) Laminated varistor
US6260258B1 (en) Method for manufacturing varistor
JPH02135702A (en) Lamination type varistor
JPH02302005A (en) Laminate-type varistor
JPH02189903A (en) Laminated varistor
JP2983096B2 (en) Manufacturing method of laminated voltage non-linear resistor
JPH11340090A (en) Manufacturing method of grain boundary insulated multilayer ceramic capacitor
JP2727789B2 (en) Positive characteristic thermistor and manufacturing method thereof
JPS62122103A (en) Manufacturing method of laminated chip varistor
JP4907138B2 (en) Chip type NTC element
JP2504226B2 (en) Stacked Varistor
JPH02220407A (en) Laminated varistor
JPH03173403A (en) Chip varistor
JPH02220408A (en) Laminated varistor
JPH02260604A (en) Lamination type varistor
JPS63219115A (en) Manufacture of laminated semiconductor porcelain electronic component
JPH02309604A (en) Laminated varistor
JP3240689B2 (en) Laminated semiconductor porcelain composition
JP3289354B2 (en) Laminated semiconductor porcelain with positive resistance temperature characteristics
JPH02220405A (en) Manufacture of laminated varistor
JPH0344004A (en) Stacked varistor
JPH04306802A (en) Laminated type varistor and manufacture thereof
JPH0273603A (en) Laminated type varistor
JPH0388304A (en) Manufacture of laminated-type varistor
JPH02260605A (en) Lamination type varistor