JPH02260733A - Pcm signal receiver - Google Patents

Abstract

PURPOSE:To improve the releazability of a timing extraction circuit in a fast PCM signal transmission system by employing a type in which the OR of a clock signal extracted at the input stage of the timing extraction circuit and an input signal is taken. CONSTITUTION:At an OR circuit 11, the OR processing of a stable f0 clock signal having constant and outputted from a limiter amplifier 6 and an input RZ signal is performed, and an output signal that is a result is inputted to a clock extraction filter 12. Therefore, the stable f0 clock signal can be obtained at the output of the clock extraction filter 12 even when the continuance of zero occurs in a reception signal. In such a way, the type in which the OR of the clock signal extracted at the input stage of the timing extraction circuit and the input signal is taken is employed. Thereby, it is possible to improve the realizability of the timing extraction circuit in the fact PCM signal transmission system even by using a low Q filter.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a PCM receiver, in particular a Gb/s
The present invention relates to a PCM signal receiving apparatus that improves the characteristics and feasibility of a timing extraction circuit so as to be able to receive high-speed transmission information.

(Conventional technology) As optical transmission technology advances, ultra-high-speed optical transmission technology using long wavelength band optical devices/single-mode fibers is being studied as a possibility for large-capacity/long-distance transmission systems. . In particular, in order to realize a broadband information communication network that provides a wide variety of services such as images, data, and voice, it is expected that optical transmission equipment will become faster and more stable. The transmission capacity of the backbone transmission system in such a wideband information communication network reaches several gigabits/second in, for example, a time division multiplex transmission system, and the optical transmitting/receiving equipment thereof is also required to have a wide band/high speed. Usually, the receiver of the transmission device is equipped with a timing circuit whose role is to provide a point in time at the center of the eye for correct identification of the equalized waveform. A timing extraction circuit is used that extracts timing components from within the code sequence itself.

FIG. 2 is a block diagram showing the configuration of a conventional PCM signal receiving device. Assume that the code format of the input signal is an NRZ code. Since NRZ codes, bipolar codes, and the like do not have timing components themselves, the timing signals are extracted using a nonlinear timing extraction method to generate clock signals.

In the circuit shown in FIG. 2, the NRZ signal input to the input terminal 1 is split into two branches, one of which is input to the identification circuit 7. On the other hand, the differentiating circuit 2 of the timing extraction circuit detects the sign change point, and the double-wave rectifier circuit 3 performs double-wave rectification to obtain f. The output signal of the 0 double wave rectifier circuit 3 for extracting the component is further applied to a resonant circuit (timing tank), and this resonant circuit extracts the f0 sine wave component (clock signal).

As a resonant circuit, since timing deviation is emphasized as an important characteristic, a surface acoustic wave filter (SAW) 4 designed with a fractional band Q of about 800 is used, taking into account temperature characteristics, aging, detuning, etc. (For surface acoustic wave filters, see “Surface Wave Devices and Their Applications,” Nikkan Kogyo Shimbun, Inc.,
The clock signal extracted by the surface acoustic wave filter 4 is applied as a timing signal to a narrowband amplifier 5, and in this narrowband amplifier 5 f. Only the clock signal components are selectively amplified. That f. The clock signal component is input to a limiter amplifier 6.

The clock signal input to the limiter amplifier 6 is input to the limiter amplifier 6 so that amplitude fluctuations due to pattern fluctuations are suppressed and the clock signal has a sufficient level as a signal level.
The signal is amplified with a high gain and supplied to the identification circuit 7 as an identification timing signal.

On the other hand, when the code format of the input signal is RZ, the signal itself has a clock component, so the input RZ signal 9 is directly applied to the surface acoustic wave filter 4, and a sine wave clock signal is extracted.

(Problem to be Solved by the Invention) The timing extraction circuit in the conventional PCM signal receiving device described above generates a clock signal with an f0 configuration in the GH2 region by using a high Q surface acoustic wave filter as a timing tank. do.

However, in this type of circuit, there is a problem in that the frequency range that can be used is limited due to problems with the fine processing of surface acoustic wave filters, and the process yield is reduced. This has the disadvantage that it also leads to a decrease in the productivity of the receiver. Further, if Q is set within the range that can be realized by a surface acoustic wave filter, there is a big problem that the ability to extract timing signals for continuous inputs of the same code is lost.

In other words, the fundamental frequency f of the surface wave excited in the surface acoustic wave filter is determined by the surface wave propagation velocity (2) of the material and the electrode pitch L, and becomes f=V/L. Therefore, when the excitation frequency is in the GH region, the surface wave propagation velocity is generally 3x
Since lO' (m/s), the electrode width is 1 μm.
As a specific example, you must create the following:
When crystal is used as the material for the substrate of a surface acoustic wave filter, the electrode width of the surface acoustic wave filter used in a 4 Gbps optical regenerator is 0.2 μm and the electrode length is 400 μm (
“Prototype of 4Gbps optical regenerative repeater” Institute of Electronics, Information and Communication Engineers,
Proceedings of the 1986 National Comprehensive Convention), and the fractional band Q obtained in boat fishing is proportional to the number of electrodes. Therefore Q=80
In the case of 0, nearly 800 electrodes are required. Furthermore, it is usually important to take into consideration the state in which the same sign continues as a received signal. Assume that "0" signals arrive continuously.The output signal of the clock extraction filter is V*exp(- πn/Q) (where ■=maximum input amplitude to the timing tank, n
: number of consecutive zero codes), that is, the amplitude decreases in an envelope shape due to consecutive zero codes.

In order to process a large number of highly precise electrodes with such a narrow width, there are limits to the miniaturization of microfabrication techniques such as photo etching and laser processing, which makes it difficult to realize surface acoustic wave filters and is difficult to achieve in the Gbps region. PC in
This makes it impossible to implement the timing extraction circuit of the M signal receiver. As described above, the conventional PCM signal receiving apparatus has problems to be solved in the frequency domain.

(Means for Solving the Problems) Means provided by the present invention to solve the above-mentioned problems are as follows:
A timing extraction circuit inputs a received signal, extracts a clock component included in the received signal, generates and outputs a timing signal synchronized with the clock signal, and extracts data included in the received signal in synchronization with the timing signal. a PCM signal receiving device comprising at least an identification circuit for identifying, an OR circuit in which the timing extraction circuit takes the received signal as one input signal, and a clock for extracting a clock signal from an output signal of the OR circuit; An extraction filter, a narrowband amplifier that receives the clock signal extracted by this clock extraction filter, a wideband amplifier that amplifies the output signal of this narrowband amplifier, and a circuit that detects the peak value of the output signal of this wideband amplifier. a limiter amplifier that limits and amplifies the amplitude of the narrowband amplifier; and a delay circuit that extracts a part of the output signal of the limiter amplifier and applies a certain time delay to it as the other input signal of the OR circuit. and an AND circuit that performs an AND process on the output signal of the limiter amplifier and the output signal of the peak value detection circuit to generate the timing signal.

(Function) In the PCM signal receiving device of the present invention, a logical sum circuit is provided at the input stage of the timing extraction circuit, the received signal is input to one side of the logical sum circuit, and the output signal of the logical sum circuit has a relatively low Q. A clock signal is extracted using a timing tank (clock extraction filter), and the clock signal obtained from the timing tank is amplified by a narrowband amplifier and a limiter amplifier, and split into two, and one signal is divided into two with a certain delay time. The output of this delay circuit is used as the other input of the OR circuit, and the peak value of the output signal of the narrowband amplifier is detected and AND processing is performed with the output signal of the limiter amplifier. In the PCM signal receiving device having the above configuration, it is possible to improve the feasibility of timing extraction in the GH2 domain, realize timing extraction that is resistant to the same code succession, and furthermore, it is possible to improve the feasibility of timing extraction in the GH2 region, and also to realize timing extraction that is resistant to the same code succession. It is possible to prevent random noise from being output to the identification circuit, and it is possible to improve the communication system.

(Example) Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a PCM signal receiving apparatus according to an embodiment of the present invention. In addition, in the following explanation, RZ (Return Toku) is used as the code format of the received signal.
zero) sign.

The RZ reception signal inputted to the input terminal 9 is inputted to the identification circuit 7 and also inputted to the OR circuit 11. This OR circuit 11 performs OR processing on the signal input from the delay circuit 13 and the RZ flaw signal, and generates a signal that is the OR of both signals. Now, assuming an initial stage as a time process,
Since the signal from the delay circuit 13 is no signal, the OR circuit 11 outputs a signal in which the signal component input to the input terminal 9 is dominant. The signal output from the OR circuit 11 is input to the lock extraction filter 12 . In the clock extraction filter 12, the center frequency is fo
It is necessary to set it to a high fractional band Q in consideration of timing deviation, detuning, etc. However, the fractional band Q should be set to a value that is achievable in the GHz region.In particular, considering aging, temperature characteristics, etc., a surface acoustic wave filter (SA) should be used as a timing tank.
It is desirable to use a W filter).

Now, in the example of FIG. 1, fo is set to 4 GHz, Q
is set to 100. If the clock extraction filter 12 is a surface acoustic wave filter whose substrate material is quartz, if the strip width and gap of the interdigital electrodes are chosen to be equal, the strip width "is about 0.2 μm, but since Q is 100, The total number of electrodes may be about 120, and such an electrode pattern can be created using normal photoetching technology.

The fo clock signal with stable characteristics extracted by the clock extraction filter 12 is applied to the narrowband amplifier 5, where only the fo clock signal component is selectively (tuned) and amplified. Therefore, in the f0 clock signal at the output end of the narrowband amplifier 5, the difference in signal level between the time of signal transmission and the time of signal interruption is large. The output signal of the narrowband amplifier 5 is branched into two and sent to a limiter amplifier 6 and a wideband amplifier 1.
4 is input. The clock signal input to the limiter amplifier 6 is amplified to a signal level sufficient to suppress amplitude fluctuations due to input turn fluctuations to the timing circuit, and its amplitude is limited. The fo clock signal output from the limiter amplifier 6 is branched into two branches, one of which is input to a delay circuit 13, and after being given a certain delay, is supplied to an OR circuit 11. Therefore, the OR circuit 11
, a signal having an fo spectrum component is always outputted as a result of performing an OR process on the stable fo clock signal inputted from the delay circuit 13 and the binary signal not inputted to the input terminal 9. The other signal branched into two is input to an AND circuit 16.

The clock signal input to the wideband amplifier 14 is amplified to a sufficient amplitude level while maintaining linearity, and is input to the peak value detection circuit 15. Since only the f0 signal is amplified in the amplified clock signal, the difference in amplitude during signal transmission and when the signal is interrupted is even larger. The peak value detection circuit 15 performs amplitude peak detection of the input clock signal, generates a DC signal, and outputs this DC signal to the AND circuit 16. The AND circuit 16 receives the clock signal (A) input from the limiter amplifier 6.
and the DC signal (B) from the peak value detection circuit 15 (X=A-B), and A=1. A stable timing signal (X) is output to the identification circuit 7 only when B=1.

Normally, it is important to take into consideration the state in which the same code continues in the received signal. Assume now that "0" signals arrive successively. The output signal of the clock extraction filter 12 has an amplitude characteristic of V*exp (-gn/Q) (where ■ = maximum input amplitude to the timing tank, n: number of consecutive zero codes), that is, consecutive zero codes. The amplitude decreases in an envelope shape. Therefore, if the OR circuit 11 is not provided and the signal at the input terminal 9 is directly input to the timing tank, the timing signal X to the identification circuit 7 will be unstable, causing errors in the communication system.

However, in the timing extraction circuit in the PCM signal receiving device of the present invention, the OR circuit 11 performs OR processing of the stable f0 clock signal output from the limiter amplifier 6 with a certain delay and the input RZ flaw signal, and the result is Since a certain output signal is input to the clock extraction filter 12, a stable fo clock signal can be obtained at the output of the clock extraction filter 12 even if consecutive zeros occur in the received signal.

In this way, by taking the logical sum of the clock signal extracted at the input stage of the timing extraction circuit and the input signal, it is possible to realize a timing extraction circuit for a high-speed PCM signal transmission system using a low-Q filter. Accordingly, it is possible to supply a stable timing signal to the identification circuit.

Furthermore, in the PCM signal receiving apparatus, in addition to the above-described continuation of the same code, there may also be a situation in which the transmission signal is completely cut off. In this case, in the conventional timing extraction circuit, the limiter amplifier amplifies the random noise and operates the discrimination circuit.
Sends out unnecessary noise onto the communication line.

The timing extraction circuit in the PCM signal receiving device of this embodiment also has a high gain limiter amplifier 6 and constitutes a feedback circuit as a timing extraction circuit, so when the transmission signal is disconnected, the output signal of the limiter amplifier 6 is A
Random noise occurs in

However, in this embodiment, the peak value detection circuit 15 performs peak value detection of the clock signal (out-of-band components are suppressed in the narrow band amplifier 5), and the AND circuit 16 detects the peak value (B). and the signal (A) output from the limiter amplifier 6 (X=A
-B), no random noise is output to the identification circuit 7.

In the explanation so far, the case where the code format of the received signal is RZ has been described, but the present invention is also effective in the case of NRZ. , after passing through the nonlinear means of the double-wave rectifier circuit 7,
Input t! along the route shown by the broken line in Figure 1. Similar functionality can be obtained by connecting to M9.

(Effects of the Invention) According to the present invention, it is possible to realize a PCM signal receiving device that operates stably even at a higher frequency than conventional devices and can be applied to a high-speed PCM signal transmission system of Gb/s. It can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional PCM signal receiving apparatus. 1.9...Input end, 8...Output end, 2...Differentiating circuit, 3...Double-wave rectifier circuit, 4...Surface acoustic wave filter, 5...Narrowband amplifier, 6 ...Limiter amplifier,
11... OR circuit, 12... Clock extraction filter, 13... Delay circuit, 7... Identification circuit, 14...
・Wideband amplifier, 15...Peak value detection circuit, 16・
・Logic product circuit.

Claims (1)

[Claims] A timing extraction circuit inputs a received signal, extracts a clock component included in the received signal, generates and outputs a timing signal synchronized with the clock signal, and extracts data included in the received signal in synchronization with the timing signal. A PCM signal receiving device comprising at least an identification circuit for identifying, an OR circuit in which the timing extraction circuit takes the received signal as one input signal, and a clock extraction filter that extracts a clock signal from an output signal of the OR circuit. a narrowband amplifier that receives the clock signal extracted by the clock extraction filter; a wideband amplifier that amplifies the output signal of the narrowband amplifier; and a circuit that detects the peak value of the output signal of the wideband amplifier. a limiter amplifier that limits and amplifies the amplitude of the narrowband amplifier; a delay circuit that extracts a part of the output signal of the limiter amplifier and applies a certain time delay to it as the other input signal of the OR circuit; A PCM signal receiving device comprising: an AND circuit that performs an AND process on the output signal of the limiter amplifier and the output signal of the peak value detection circuit to generate the timing signal.