JPH0321133A - Timing extracting circuit - Google Patents

Abstract

PURPOSE:To expand the high frequency band limit of frequency to be processed and to improve the realization of a timing extracting circuit in a high speed PCM signal transmission system by providing a timing extracting circuit with an OR circuit, a timing extracting filter, a limiter amplifier, and a delay circuit. CONSTITUTION:An RZ receiving signal inputted to an input terminal 9 is inputted to the OR circuit 22, OR processing between the input signal and a signal outputted from the delay circuit 26 is executed and then the result is outputted to the timing extracting filter 24. The filter 24 extracts a timing signal by means of a timing tank with comparatively low Q and outputs a clock signal f0 having stable caracteristics to the limiter amplifier 25. The amplifier 25 suppresses/amplifies amplitude variation due to pattern variation and outputs the result from an output terminal 4. At this time, the clock signal f0 is branched, supplied to the circuit 22 through the circuit 26 and set up so that the phase variation directions to temperature in the filter 24 and the amplifier 25 are positively/negatively chanceled. Consequently, the high range limit of frequency to be processed can be expanded and the realization of the timing extracting circuit in the high speed PCM signal transmission system can be improved.

Description

[Detailed Description of the Invention] (Field of Application in Industry) The present invention relates to a timing extraction circuit for a PCM signal receiving device, and particularly to the characteristics and feasibility of a timing extraction circuit in a high-speed information transmission system called Gb/s. This invention relates to an improved timing extraction circuit.

<Conventional technology> With the advancement of optical transmission technology, studies are progressing on ultra-high-speed optical transmission technology using long wavelength band optical devices/single mode fibers as a possibility for large-capacity/long-distance transmission systems.
In particular, in order to realize a broadband information communication network that provides a wide variety of services such as images, data, and reputation, it is expected that optical transmission equipment will become faster and more stable.

The transmission capacity of the backbone transmission system in such a broadband information communication network reaches several gigabytes per second in a time division multiplex transmission system, for example, and the optical transmitting/receiving equipment thereof is also required to have a wide band/high speed.

Normally, the receiver of a transmission device is equipped with a timing circuit that provides the center point of the eye in order to correctly identify the equalized waveform. A timing extraction circuit is used to extract timing precepts from the code sequence itself.

FIG. 5 is a block diagram of a conventional timing extraction circuit. Assume that the code format of the input signal is an NRZ code. Since NRZ codes, bipolar codes, and the like do not have their own timing components, devices that receive these codes generally extract timing signals using a nonlinear timing extraction method to generate clock signals.

In FIG. 5, the NRZ signal input to the input terminal A1 is subjected to a sign change point detection in a differentiating circuit 6, and is subjected to double-wave rectification in a double-wave rectifier circuit 7 to extract a certain amount of fO. The output signal of the double-wave rectifier circuit 7 is further applied to a resonant circuit (timing tank) to extract the fo sine wave component (clock signal). As a resonant circuit, a surface acoustic wave filter (SAW) designed with a fractional band Q of around 800 is used, taking into account temperature characteristics, aging, M-key, etc., as timing deviation is considered an important characteristic. ``Surface Wave Devices and Their Applications'', Nikkan Kogyo Shimbun). On the other hand, when the input signal code format is RZ, the signal itself has a clock component, so the input signal 9 in the figure is directly passed through the surface acoustic wave filter. 8 to extract a sinusoidal clock signal.

(Problem to be Solved by the Invention) Such a conventional timing extraction circuit uses a high Q surface acoustic wave filter as a timing tank, and
A clock signal of the fO component in the z domain is generated. However, in this type of timing extraction circuit, there is a limit to the frequency range that can be used due to limitations in microfabrication of the surface acoustic wave filter, and the process yield is reduced. It also leads to a decrease in productivity of a PCM signal receiver using the conventional timing extraction circuit.

Also, if a surface acoustic wave filter can be realized, the Q
When used with this setting, there was a major problem in that the ability to extract timing signals for consecutive inputs of the same code was lost.

3. That is, at the fundamental frequency of the surface wave excited in the surface acoustic wave filter, f=V/L, which is determined by the surface wave propagation velocity (■) of the material and the electrode pitch L. Therefore, when the excitation frequency is in the GHz region, the surface wave propagation velocity is generally 3
X1.03 (m/s), so the electrode width is 1μ
m or less must be created. As a specific example, the electrode width of a surface acoustic wave filter used in a 4Gbps optical regenerator is 0.2 μm using a crystal substrate as the material.
, the electrode length is 400 μm (``Prototype production of 4 Gbps optical regenerative repeater'', Institute of Electronics, Information and Communication Engineers, 1986 National Conference Proceedings).In addition, the generally obtained fractional bandwidth Q is proportional to the number of electrodes. Therefore, if Q = 800, the number of electrodes will be close to 800. 6 Furthermore, it is important to take into consideration that the reception signal is usually of the same sign or is continuous. Assume that '0'' signals arrive continuously.The output signal of the timing extraction filter has an amplitude characteristic of V*exp (-πn/Q) (here,
V: maximum input amplitude to the timing tank, 4 n: number of consecutive zero codes). That is, the amplitude decreases along the envelope line due to the succession of zero codes.

In order to process a large number of such electrode widths with high precision, there are limits to processing techniques such as hole etching and laser processing, which makes it difficult to realize surface acoustic wave filters and to reduce PCM signals in the Gbps region. This makes it impossible to implement the receiver's timing extraction circuit. As described above, the conventional timing extraction circuit has a problem to be solved regarding the Takagi limit of the frequency to be handled.

(Means for Solving the Problems) In order to solve the above-mentioned problems, a timing extraction circuit according to the present invention includes an OR circuit whose one input is a received signal, and a stable output signal from the output signal of the OR circuit. a timing extraction filter that extracts a timing signal; a limiter amplifier that receives the output signal of the timing extraction filter as an input; and a limiter amplifier that applies a certain time delay to the output signal of the limiter amplifier and connects it to the other input signal of the OR circuit. The timing extraction filter and the six liminter amplifiers 2K have phase fluctuations in directions opposite to each other with respect to temperature, and the amounts of the phase fluctuations are set to be approximately equal.

(Function) In the present invention described above, an OR circuit is provided at the input stage, and after extracting a timing signal from the output signal 8 of the OR circuit using a timing tank with relatively low Q, the timing extraction signal is The GH
7. It is possible to improve the feasibility of realizing a timing extraction circuit that corresponds to the region, and also to realize a timing extraction circuit that is resistant to the same code sequence. By setting the fluctuation direction to cancel the positive and negative, fluctuations in the phase of the input timing signal to the identification circuit are reduced, and the phase between the input signals in the OR circuit is always kept constant, improving communication system performance. Something will happen.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a timing extraction circuit according to an embodiment of the present invention. In addition, in the following explanation, RZ (Return to Zero) is used as the code format of the received signal.
Assume the sign.

The RZ reception signal input to the input terminal 9 is input to the OR concave path 22. The OR circuit 22 performs an OR process on the signal input from the delay circuit 26 and the input signal to the timing circuit, and generates an output signal.

Now, assuming the initial stage as a time process, the delay time f%2
Since the f word from 6 is a non-signal, the logic sum circuit 22 outputs a signal in which the signal component input to the input terminal 9 is dominant.

The signal output from the OR circuit 22 is input to the timing extraction filter 24. Timing extraction filter 2
Considering the fact that the center frequency of 4 is set to fO, timing deviation, detuning, etc., is it necessary to set it to a high fractional band Q?Is it necessary to set the center frequency to a high frequency band Q that can be realized in the GHz region? is good.

In particular, considering aging, temperature characteristics, etc., it is desirable to use a surface acoustic wave filter (SAW filter) as the timing tank.

Now, in Figure 1, set fO to 4GHz. Let Q be 100. If the timing extraction filter 24 is a surface acoustic wave filter made of crystal, and the strip width and gap of the interdigital electrodes are selected to be equal, the strip width will be approximately 0.2.
μm, but Q is 100, so the total number of electrodes may be about 120, and such an electrode pattern can be created by normal photo-etching technology.

The fO clock signal with stable characteristics extracted by the timing bolt I1 filter 24 is sufficiently amplified in the limiter amplifier 25 to suppress amplitude fluctuations due to pattern fluctuations and to avoid insertion loss of the timing extraction filter 24. It is output from the rear output end 4. Moreover, this stable fO clock signal is simultaneously branched and inputted to the delay circuit 26, and after being given a certain delay, it is sent to the logical OR concave circuit 26.
2.

Therefore, the output signal of the OR circuit 22 is always the rO spec as a result of ORing the stable rO clock signal input from the delay circuit 26 and the binary signal input to the input terminal 9. A signal having components 1 to 1 is output.

Normally, it is important to take into consideration the same sign or consecutive states as received (2 signals B). Now, suppose that the ゜゛0'' signal arrives consecutively. The output signal of the timing extraction filter 24 is V* The amplitude characteristic is exp(-πn/Q) (where ■=maximum input amplitude to the timing tank,
■: Consecutive number of seven ro codes).

That is, the amplitude decreases in an envelope shape due to the continuation of the seven lo signs.

Therefore, if the OR concave path 22 is not provided and the signal at the input terminal 9 is input directly to the timing tank, the timing signal at the output terminal 4 will become unstable, leading to errors in the communication system.

However, in the timing extraction circuit of the present invention, the logical sum #l
22, the stable fO timing signal after a certain delay and the input RZ signal are logically ORed, and the resulting output signal is input to the timing extraction filter 24, so even if consecutive zeros occur in the received signal, A stable fO clock signal is obtained at the output end 4.

An important point in the present invention is the temperature characteristics of the timing extraction filter 24 and limiter amplifier 25.

When the limiter amplifier 25 is realized with a semiconductor device, its phase temperature characteristics are determined by the circuit ellipse and process.
Normally, the characteristics are as shown in FIG.

It is extremely difficult to obtain a zero temperature coefficient with this alone.

On the other hand, when the timing extraction filter 24 is realized by a surface acoustic wave device, its phase temperature characteristics are determined by the type of base material through which the surface acoustic wave propagates, the cutting angle, and the phase inclination of the filter.

Therefore, it is possible to realize a surface acoustic wave filter having a phase temperature characteristic opposite to that of the limiter amplifier 25 as shown in FIG.

In the timing extraction circuit according to the present invention, by using this surface acoustic wave filter as the timing extraction filter 24, as shown in FIG. (c) can be realized as the phase temperature characteristic as a timing extraction circuit by mutually correcting by (b).

In this way, by taking the logical sum of the timing signal extracted at the input stage of the timing extraction circuit and the input signal, it is possible to reduce the possibility of realizing the timing extraction u1 circuit of the high-speed PCM (i3 transmission system). A Q filter can also be used to provide an improved and stable clock signal to the identification circuit.

Furthermore, by using a timing extraction filter and a limiter amplifier whose phase fluctuations with respect to temperature are in opposite directions or opposite to each other and whose fluctuation amounts are the same, it is possible to realize a timing extraction circuit that makes the temperature coefficient with respect to the phase almost zero. I can do it.

In the explanation so far, the code format of the received signal or RZ
Although we have described the case of NRZ, the present invention is also effective in the case of NRZ, and after passing through the nonlinear means of the differential circuit 6 and the double-wave rectifier circuit 7 as in the conventional example shown in FIG. Similar functionality is obtained by connecting to input @9.

(Effects of the Invention) As described above, if the timing extraction circuit according to the present invention is used, the processing precision required for surface acoustic wave filters is relaxed, and the Takagi limit of frequencies to be handled is expanded, making timing extraction in high-speed PCM signal transmission systems possible. The feasibility of the circuit can be significantly improved.

1.9...Input end, 4...Output end, 6...Differential circuit, 7...Double wave rectifier circuit, 8...Surface acoustic wave filter, 22...Logical phase circuit, 24...Timing extraction filter, 25...Limiter amplifier, 26...Delay circuit.

Claims (1)

[Claims] an OR circuit that takes a received signal as one input signal; a timing extraction filter that extracts a stable timing signal from the output signal of the OR circuit; a limiter amplifier that takes the output signal of the timing extraction filter as input; a delay circuit that applies a certain time delay to the output signal of the limiter amplifier and uses it as the other input signal of the OR circuit, and the timing extraction filter and the limiter amplifier have phase fluctuations in directions opposite to each other with respect to temperature. A timing extraction circuit characterized in that the amounts of phase fluctuations are set approximately equal.