JPH0226319B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory drive circuit that performs data write operations or bit operations on semiconductor memories.

FIG. 1 shows a conventional example of a semiconductor memory cell composed of MOS type transistors (hereinafter referred to as transistors). The semiconductor memory cell 5 includes transistors 1 and 2 that operate as transfer gates, and inverter circuits 3 and 4. The gates of transistors 1 and 2 are connected to address line 6, and address line 6 is “1”.
(high level), transistors 1 and 2 are in a conductive state, and when address line 6 is "0" (low level), transistors 1 and 2 are in a non-conductive state. Further, one terminal of transistors 1 and 2 is connected to a digital line 7 to which a data signal is input.
and 7', respectively.

In FIG. 1, the address line 6 is "1"
When transistors 1 and 2 are in a conductive state, when "1" is input to digit line 7 and "0" is input to digit line 7', "1" is stored in the semiconductor memory cell. Also, when "0" is input to the digit line and "1" is input to the digit line 7', "0" is stored in the semiconductor memory cell. If digit lines 7 and 7' are open, the contents of the semiconductor memory cell will be retained even if address line 6 is "1". Note that when the address line 6 is "0", the transistors 1 and 2 are rendered non-conductive, so that the contents of the semiconductor memory cell are retained.

As shown in FIG. 2, a semiconductor memory device 8 constituted by multi-bit semiconductor memory cells has a plurality of gates of transistors 1 and 2 of the memory cells connected to an address line 6, and digit lines 7 and 7'. can be configured in a matrix by connecting a plurality of one terminals of each of the transistors 1 and 2 of the memory cell.

The semiconductor memory described above is used as internal memory of microcomputers and their peripheral devices, and
Widely used as external memory. Conventionally, when performing a bit set or bit reset on the contents of such a semiconductor memory, a predetermined address line is set to "1", the contents of the specified semiconductor memory are read once, and then the bits are reset to the read contents. After performing an operation, the result of the operation had to be written to the semiconductor memory again. Therefore, when performing a bit set or reset on the contents of the semiconductor memory, the processing time of the data write operation is shorter than the data write operation. Reading the contents of the semiconductor memory and performing bit manipulation processing requires at least twice as much processing time, and in addition, a special logic operation circuit, etc. is required to perform bit manipulation on the contents read from the semiconductor memory. was needed.
Therefore, when implementing a device having data write operation and bit manipulation functions for a semiconductor memory using a semiconductor integrated circuit, there are disadvantages such as an increase in cost due to an increase in the number of transistor elements.

The present invention was invented in view of the above circumstances, and it performs a bit set or a write operation on the contents of the semiconductor memory in a time equal to the processing time of the data write operation to the semiconductor memory as well as the data write operation to the semiconductor memory. A memory drive circuit that can perform a bit reset operation with a very simple circuit configuration is provided. In particular, by adding the memory drive circuit according to the present invention to a semiconductor device that is mainly a semiconductor memory and does not require a special logic operation circuit (for example, a display device equipped with a display memory), Executes a data write operation and also performs a bit set or reset operation on the contents of the semiconductor memory in the same time as writing data to the semiconductor memory.
This can be easily carried out, and furthermore, since a special logical operation circuit for performing bit set and bit reset operations is not required, it is possible to provide a functionally superior semiconductor device with a small number of transistor elements.

According to the present invention, a pair of first and second digit lines are connected to memory cells constituting a memory cell array, and input information is transmitted to a memory cell selected by an address signal via the first and second digit lines. In a memory circuit for storing data, a data line to which data is input, a first control line to which a first control signal is input, a second control line to which a second control signal is input, and a first a first potential supply means for supplying a potential, and a second potential supply means for supplying a second potential.
is coupled to the first potential supply means, the data line, and the first and second control lines, and when the data line is in the first state and the first control signal is in the first state; The first potential is applied only to the first digit line that supplies the selected memory cell, and the first potential is selected only when the data line is in the second state and the second control signal is in the first state. means for applying a potential to a second digit line connected to a memory cell connected to the second state; and a second potential supply means coupled to the data line and the first and second control lines; A second potential is applied to the first digit line connected to the selected memory cell only when the second control signal is in the first state, and the first control signal is in the first state while the data line is in the first state. and means for applying a second potential to a second digit line connected to a selected memory cell only when the selected memory cell is in the state.

An embodiment according to the present invention will be described with reference to FIG.

Using memory drive circuits 23.1 to 23.4,
A configuration diagram showing a data write operation, a bit set operation, and a bit reset operation executed in units of 4 bits is shown. Data is input from the 4-bit bus line 24 to data lines 21.1 to 21.4. The memory drive circuit 23 according to the present invention is connected to each digit line pair of the semiconductor memory device 8 to perform data write operations and bit operations on multiple bit semiconductor memory cells connected on the digit line pair. be able to. In the example shown in the figure, the data write operation and bit manipulation are executed in units of 4 bits.
Can be expanded to any bit unit. Fourth
In FIG. 3, address lines 6.m are used as address lines, and digit lines 7.1,
A specific example of a semiconductor memory cell having a digit line 7'.1 and a memory drive circuit 23 according to the present invention connected to the digit lines 7.1 and 7'.1 is shown.

Although this figure shows a specific example of the present invention configured with complementary MOS transistors, it is also applicable to a configuration with n-channel type or p-channel type MOS transistors by performing appropriate logic conversion. In addition, in the same figure, the first
Means that are the same as in the figures are given the same numbers.

In FIG. 4, transistors 1, 2, 10 and 11 are n-channel transistors, transistors 9 and 12 are p-channel transistors, and inverter circuits 3, 4, 19, 2
0, 22, AND circuits 13 and 14, and OR circuits 15 and 16 are composed of complementary transistors. The gates of transistors 9 and 12 are connected to the outputs of OR circuits 15 and 16, respectively, and the sources of transistors 9 and 12 are connected to
Connected to GND (ground). The gates of transistors 10 and 11 are connected to the outputs of AND circuits 13 and 14, respectively, and transistor 1
The source side of 0 and 11 is +V (high level voltage)
It is connected to the. The drain sides of transistors 9 and 10 are connected to the digit line 7.1 of the semiconductor memory cell, and the drain sides of transistors 11 and 12 are connected to the digit line 7'.1. Control lines 17 and 18 are control lines that specify four states: data write, bit set, bit reset, and data retention. Control line 17 is input to AND circuit 14 and inverter circuit 19, and output from inverter circuit 19 teeth,
It is input to the OR circuit 15. The control line 18 is
It is input to an AND circuit 13 and an inverter circuit 20, and the output of the inverter circuit 20 is input to an OR circuit 16. A data line 21 to which data is input is input to an AND circuit 13, an OR circuit 15, and an inverter circuit 22, and an output of the inverter circuit 22 is input to an AND circuit 14 and an OR circuit 16.

Next, the operation shown in FIG. 4 will be explained. Now, the address line 6.m is "1", and the semiconductor memory cell 5
Assume that the data write operation is possible. First, for the semiconductor memory cell 5,
A case in which data input to the data line 21 is written will be described. In this case control lines 17 and 18
is set to “1”. When data "1" is input to the data line 21, the outputs of the AND circuit 13 and the OR circuit 15 become "1", and the outputs of the AND circuit 14 and the OR circuit 15 become "0".
Since transistors 10 and 12 become conductive, +V (hereinafter referred to as "1") is applied to digital lines 7 and 1.
Since GND (hereinafter referred to as "0") is transmitted to the digit line 7', 1, "1" is stored in the semiconductor memory cell 5.
Furthermore, when data "0" is input to the data line 21, the outputs of the AND circuit 13 and the OR circuit 15 become "0", and the outputs of the AND circuit 14 and the OR circuit 16 become "1". Transistors 9 and 1
1 becomes conductive, so "0" is transmitted to the digit line 7.1, and "1" is transmitted to the digit line 7'.1, so the semiconductor memory cell 5
“0” is stored in .

Next, when performing a bit set operation on the semiconductor memory cell 5, the control line 17 is set to "0",
The control line 18 is designated as "1". data line 21
When data "1" is input, the outputs of the AND circuit 13 and the OR circuit 15 become "1", and the outputs of the AND circuit 14 and the OR circuit 16 become "0", so that the transistors 10 and 12 It becomes conductive, and "1" is stored in the semiconductor memory cell 5. Furthermore, when data "0" is input to the data line, the outputs of AND circuits 13 and 14 become "0" and the outputs of OR circuits 15 and 16 become "1", so transistors 9 and 10 ,11
and 12 become non-conductive, digit lines 7.1 and 7'.1 become open, and semiconductor memory cell 5 retains the previous data. Therefore, when the control line 17 is designated as "0" and the control line 18 is designated as "1", "1" is stored in the selected semiconductor memory only when "1" is input to the data line. Bitset operations can be performed.

Next, when performing a bit reset operation on the semiconductor memory cell 5, the control line 17 is designated as "1" and the control line 18 is designated as "0". When data "1" is input to the data line 21, the outputs of the AND circuits 13 and 14 are "0", and the output of the OR circuit 15 is "0".
Since the outputs of and 16 become "1", transistors 9, 10, 11 and 12 all become non-conductive, and semiconductor memory cell 5 retains the previous data. Furthermore, when data "0" is input to the data line, the outputs of the AND circuit 13 and the OR circuit 15 become "0", the outputs of the AND circuit 14 and the OR circuit 16 become "1", and the transistors 9 and 11 becomes conductive, "0" is transmitted to digit line 7.1, and "1" is transmitted to digit line 7'.1, so that "0" is stored in semiconductor memory cell 5. Therefore, when the control line 17 is specified as "1" and the control line 18 is specified as "0", "0" is stored in the selected semiconductor memory only when "0" is input to the data line, and the bit reset is performed. can perform actions.

Note that when data is not written to the semiconductor memory, the control lines 17 and 18 may be set to "0".

Memory drive circuit 2 according to the invention in FIG.
3, transistors 9 to 12 and an AND circuit 13
and 14, OR circuits 15 and 16, a control line, and a data line. In particular, transistors 9 to 12 are originally necessary circuits for driving the digital line of a semiconductor memory, and the present invention 17 and 18, transistors 9, 1
With a simple circuit configuration that only controls 0, 11, and 12, it can be used for semiconductor memory as explained above.
Bit manipulation is also possible.

Furthermore, in the bit reset operation, the semiconductor memory selected only when the data on the data line is "1" stores "1", and in the bit reset operation, the semiconductor memory selected only when the data on the data line is "0". Since "0" is stored in semiconductor memory,
It has the same effect as performing an OR operation or an AND operation between the contents of a semiconductor memory and data, and is used as an OR operation or an AND operation function between the contents of a semiconductor memory and data in a microcomputer, etc. It is also possible.
The above operation is performed by a drive circuit 23' having complementary transistors 24 to 31 connected in series, as shown in FIG.
But it can be done.

As described above, with the memory drive circuit according to the present invention, it is possible to perform a data write operation, a bit set operation, or a bit reset on a semiconductor memory by adding a very simple circuit. The processing time for the semiconductor memory can be reduced by using the memory drive circuit according to the present invention in a semiconductor device having a semiconductor memory. This has very great effects, such as being able to prevent an increase in the number of transistor elements due to the operation function, and providing a semiconductor device that is low in cost and has excellent functionality.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a semiconductor memory cell.
FIG. 2 is a diagram showing a semiconductor memory array, and FIG. 3 is a diagram showing a 4-bit memory operation configuration according to the present invention.
4 and 5 are diagrams showing respective embodiments of the memory drive circuit according to the present invention. 17, 18... control line, 19, 20, 22...
Inverter circuit, 21...Data line, 24-31
...transistor, 23, 23'...memory drive circuit according to the present invention.

Claims (1)

[Claims] 1. A memory circuit in which a pair of first and second digit lines are connected to memory cells forming a memory cell array, and input information is stored in a memory cell selected by an address signal via the first and second digit lines. , a data line to which data is input, a first control line to which a first control signal is input, a second control line to which a second control signal is input, and a first potential is supplied. a first potential supply means, a second potential supply means for supplying a second potential, a second potential supply means coupled to the first potential supply means, the data line, and the first and second control lines; line is in a first state and said first control signal is in a first state.
Applying the first potential to the first digit line that supplies the selected memory cell only when the data line is in the second state and the second control signal is in the first state. means for applying the first potential to a second digit line connected to a selected memory cell; The second potential is applied to the first digit line connected to the selected memory cell only when the data line is in the second state and the second control signal is in the first state. In the state of
and means for applying the second potential to a second digit line connected to a selected memory cell only when a control signal of the memory cell is in a first state.