JPH0226320B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory drive circuit that performs data write operations or bit operations on semiconductor memories.

FIG. 1 shows a conventional example of a semiconductor memory cell composed of MOS type transistors (hereinafter referred to as transistors). The semiconductor memory cell 5 includes a transistor 1 that operates as a transfer gate.
and 2, and inverter circuits 3 and 4. The gates of transistors 1 and 2 are connected to address line 6, and when address line 6 is "1" (high level), transistors 1 and 2 are connected to address line 6.
becomes conductive, and address line 6 becomes “0”
(low level), one terminal of transistors 1 and 2 is connected to digit lines 7 and 7', respectively, into which data signals are input.

In FIG. 1, the address line 6 is "1"
When transistors 1 and 2 are in a conductive state, when "1" is input to digit line 7 and "0" is input to digit line 7', "1" is stored in the semiconductor memory cell. Also, when "0" is input to the digit line and "1" is input to the digit line 7', "0" is stored in the semiconductor memory cell. If digit lines 7 and 7' are open, the contents of the semiconductor memory cell will be retained even if address line 6 is "1". Note that when the address line 6 is "0", the transistors 1 and 2 are rendered non-conductive, so that the contents of the semiconductor memory cell are retained.

As shown in FIG. 2, a semiconductor memory device 8 constituted by multi-bit semiconductor memory cells has a plurality of gates of transistors 1 and 2 of the memory cells connected to an address line 6, and digit lines 7 and 7'. can be configured in a matrix by connecting a plurality of one terminals of each of the transistors 1 and 2 of the memory cell.

The semiconductor memory described above is used as internal memory of microcomputers and their peripheral devices, and
Widely used as external memory. Conventionally, when performing a bit set or bit reset on the contents of such a semiconductor memory, a predetermined address line is set to "1", the contents of the specified semiconductor memory are read once, and then the bits are reset to the read contents. After performing an operation, the result of the operation had to be written to the semiconductor memory again. Therefore, when performing bit set or bit reset on the contents of semiconductor memory, the processing time is at least twice as long as the data write operation processing time because the semiconductor memory contents are read and bit manipulation processing is executed. In addition, a special logic operation circuit or the like was required to perform bit operations on the contents read from the semiconductor memory.
Therefore, when implementing a device having data write operation and bit manipulation functions for a semiconductor memory using a semiconductor integrated circuit, there are disadvantages such as an increase in cost due to an increase in the number of transistor elements.

The present invention was invented in view of the above circumstances, and it performs a bit set or a write operation on the contents of the semiconductor memory in a time equal to the processing time of the data write operation to the semiconductor memory as well as the data write operation to the semiconductor memory. A memory drive circuit that can perform a bit reset operation with a very simple circuit configuration is provided. In particular, by adding the memory drive circuit according to the present invention to a semiconductor device that is mainly a semiconductor memory and does not require a special logic operation circuit (for example, a display device equipped with a display memory), Executes a data write operation and also performs a bit set or reset operation on the contents of the semiconductor memory in the same time as writing data to the semiconductor memory.
This can be easily carried out, and furthermore, since a special logical operation circuit for performing bit set and bit reset operations is not required, it is possible to provide a functionally superior semiconductor device with a small number of transistor elements.

According to the present invention, the first and second digit lines connected to the memory cell and forming a pair, and the first digit line connected in series between the first node and the first power supply potential. first and second transistors of a conductivity type; third and fourth transistors of a second conductivity type connected in series between the first node and a second power supply potential; a first connecting means for connecting the node to the first digit line; fifth and sixth transistors of a first conductivity type connected in series between the second node and the first power supply potential; , seventh and eighth transistors connected in series between the second node and the second power supply potential;
a second connection means for connecting the second node to the second digit line; and a first connection means for providing the first control information.
a second control information supply means for supplying inverted information of the first control information, a third control information supply means for supplying the second control information, and a second control information supply means for supplying the second control information; a fourth control information supply means for supplying inversion information of information; an input information supply means for supplying input information; an inversion input information supply means for supplying inversion information of input information; and a first control information supply means. means for connecting to the gate of the eighth transistor; means for connecting the second control information supply means to the gate of the first transistor; and means for connecting the third control information supply means to the gate of the fourth transistor. means for connecting the fourth control information supply means to the gates of the fifth transistor; means for connecting the input information supply means to the gates of the second and third transistors;
and means for connecting to the gate of the seventh transistor.

A configuration example in which the present invention is used will be explained with reference to FIG.

The figure uses memory drive circuits 23.1 to 23.4 to write data in units of 4 bits.
This is an example of a configuration for executing a bit set operation and a bit reset operation. Data is input from the 4-bit bus line 24 to data lines 21.1 to 21.4. A memory drive circuit 23 using an embodiment of the present invention, which will be described later, is connected to each digit line pair of the semiconductor memory device 8 to write data to a plurality of bits of semiconductor memory cells connected on the digit line pair. Operations and bit operations can be performed. In the example in the same figure, 4
Although this is an example in which data write operations and bit operations are performed in units of bits, it can be extended to any unit of bits.

In FIG. 4, in FIG. 3, the address line 6.
m is the address line, and digital line 7.
A semiconductor memory cell with digit lines 1, 7', 1 and a memory drive circuit 23 according to an embodiment of the present invention connected to the digit lines 7, 1, 7', 1.
shows.

This figure shows a specific example of the present invention constructed from complementary MOS transistors. In this figure, the same means as in FIG. 1 are given the same numbers.

In FIG. 4, transistors 26 to 29 are n-channel transistors, transistors 24, 25, 30, and 31 are p-channel transistors, and inverter circuits 19, 20,
22 is composed of complementary transistors. The gates of the transistors 24 and 31 are connected to the outputs of the inverter circuits 19 and 20, respectively, and the sources of the transistors 24 and 31 are connected to the outputs of the inverter circuits 19 and 20, respectively.
Connected to GND (ground). The gates of transistors 27 and 28 are connected to control line 18, respectively.
and 17, and the sources of transistors 27 and 28 are connected to +V (high level voltage). A transistor 2 is connected in series between these transistors 24, 27 and 28, 31.
5, 26 and 29, 30 are connected to each other, and the drain sides of transistors 24 and 27 are connected to each other.
The transistors 25 and 26 are connected to the digital lines 7 and 1 of the semiconductor memory cells, and the drain sides of the transistors 28 and 31 are connected to the transistor 2.
It is connected to the digit line 7'.1 via 9 and 30. Control lines 17 and 18 are control lines for specifying four states: data write, bit set, bit reset, and data retention, and control line 17 is connected to transistor 28 and inverter circuit 1
The output of the inverter circuit 19 is input to the transistor 24. The control line 18 connects the transistor 27 and the inverter circuit 2
0, and the output of the inverter circuit 20 is input to the transistor 31. The data line 21 to which data is input is connected to the transistor 2
5, 26 and an inverter circuit 22, and the output of the inverter circuit 22 is input to transistors 29 and 30.

Next, the operation shown in FIG. 4 will be explained. Now, the address line 6.m is "1", and the semiconductor memory cell 5
Assume that the data write operation is possible. First, for the semiconductor memory cell 5,
A case in which data input to the data line 21 is written will be described. In this case control lines 17 and 18
is set to “1”. When data “1” is input to the data line 21, the transistor 26
and the gate of 27 becomes “1”, and the transistor 3
Since the gates of 0 and 31 become "0", transistors 26, 27, 30 and 31 become conductive, and +V (hereinafter referred to as "1") is applied to digital lines 7 and 1.
Since GND (hereinafter referred to as "0") is transmitted to the digit line 7', 1, "1" is stored in the semiconductor memory cell 5.
Furthermore, when data "0" is input to the data line 21, the gates of transistors 24 and 25 become "0" and the gates of transistors 28 and 29 become "1", so transistors 9, 24, 2
5, 28, and 29 are in a conductive state, "0" is transmitted to the digit lines 7 and 1, and "1" is transmitted to the digit lines 7' and 1, so that the semiconductor memory cell 5 is transmitted with a "0". is memorized.

Next, when performing a bit set operation on the semiconductor memory cell 5, the control line 17 is set to "0",
The control line 18 is designated as "1". data line 21
When data "1" is input, the gates of transistors 26 and 27 become "1" and the gates of transistors 30 and 31 become "0", so transistors 26, 27, 30, and 31 become conductive. , "1" is stored in the semiconductor memory cell 5. Further, when data "0" is input to the data line, transistors 26, 30, 28, 24
becomes non-conductive, digital lines 7.1 and 7'.1 become open, and semiconductor memory cell 5
retains previous data. Therefore, when the control line 17 is designated as "0" and the control line 18 is designated as "1", "1" is stored in the selected semiconductor memory only when "1" is input to the data line. Bitset operations can be performed.

Next, when performing a bit reset operation on the semiconductor memory cell 5, the control line 17 is designated as "1" and the control line 18 is designated as "0". When data "1" is input to the data line 21, the transistors 25, 29, 27, and 31 all become non-conductive, and the semiconductor memory cell 5 retains the previous data. Furthermore, when data "0" is input to the data line, transistors 25 and 24 become conductive, and "0" is transmitted to digital lines 7 and 1, while transistors 28 and 29 become conductive. Since "1" is transmitted to digit line 7'.1, "0" is stored in semiconductor memory cell 5. Therefore, when the control line 17 is specified as "1" and the control line 18 is specified as "0", "0" is stored in the selected semiconductor memory only when "0" is input to the data line, and the bit reset is performed. can perform actions.

Note that when data is not written to the semiconductor memory, the control lines 17 and 18 may be set to "0".

Memory drive circuit 2 according to the invention in FIG.
3 is composed of transistors 24 to 31, inverter circuits 19, 20, and 22, a control line, and a data line, but in particular, transistors 25, 2
Reference numerals 6, 29, and 30 are circuits that are essentially necessary to drive the digital lines of the semiconductor memory.
With a simple circuit configuration that only controls the bits 4, 27, 28, and 31, it is possible to perform bit operations on the semiconductor memory as described above.

Furthermore, in the bit reset operation, the semiconductor memory selected only when the data on the data line is "1" stores "1", and in the bit reset operation, the semiconductor memory selected only when the data on the data line is "0". Since "0" is stored in semiconductor memory,
It has the same effect as performing an OR operation or an AND operation between the contents of a semiconductor memory and data, and is used as an OR operation or an AND operation function between the contents of a semiconductor memory and data in microcomputers, etc. It is also possible to do so.

As described above, the memory drive circuit according to the present invention makes it possible to perform a data write operation, a bit set operation, or a bit reset operation on a semiconductor memory by adding a very simple circuit. The operation time is equal to the processing time of the data write operation, and by using a semiconductor memory drive circuit, the processing time for the semiconductor memory can be shortened.Furthermore, the number of transistor elements can be reduced by having a bit manipulation function in the semiconductor device. The effects are very large, such as being able to prevent an increase in the number of semiconductors and providing a low-cost semiconductor device with excellent functionality.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a semiconductor memory cell.
FIG. 2 is a diagram showing a semiconductor memory array, FIG. 3 is a diagram showing a 4-bit memory operation configuration using the present invention, and FIG. 4 is a diagram showing a memory driving circuit according to an embodiment of the present invention. 17, 18... control line, 19, 20, 22...
Inverter circuit, 21...Data line, 24-31
...Transistor, 23...Memory drive circuit according to the present invention.

Claims (1)

[Claims] 1. The first wire is connected to the memory cell and forms a pair of two wires.
and a second digit line, first and second transistors of a first conductivity type connected in series between the first node and the first power supply potential, and the first node and the second transistor connected in series. third and fourth transistors of a second conductivity type connected in series between the power supply potential of the first digit line; first connecting means for connecting the first node to the first digit line; the fifth and sixth transistors of the first conductivity type connected in series between the second node and the first power supply potential, and the second node and the second power supply potential; seventh and eighth transistors connected in series to the second digit line; second connecting means for connecting the second node to the second digit line; and first control information for providing first control information. supplying means, a second control information supplying means supplying inverted information of the first control information, and a third control information supplying means supplying the second control information.
a fourth control information supply means for supplying inversion information of the second control information, an input information supply means for supplying input information, and an inversion input for supplying inversion information of the input information. information supply means; means for connecting the first control information supply means to the gate of the eighth transistor;
means for connecting the control information supply means to the gate of the first transistor; means for connecting the third control information supply means to the gate of the fourth transistor; and the fourth control information supply means. means for connecting to the gate of the fifth transistor;
It is characterized by comprising means for connecting the input information supply means to the gates of the second and third transistors, and means for connecting the inverted input information supply means to the gates of the sixth and seventh transistors. memory circuit.