JPH022649A - Analysis of trouble of semiconductor device - Google Patents

Abstract

PURPOSE:To observe a very small potential difference with ease by partly removing passivation and interlayer insulating films only on each layer conductor wiring and analyzing the surface of each layer conductor wiring exposed by anisotropic etching with use of an electron beam tester using a stroboscopic SEM. CONSTITUTION:Interlayer insulating film 4 of a multi-layer conductor wiring and a passivation insulating film 4, which are formed on a semiconductor integrated circuit including on its principal surface a diffusion layer of a semiconductor element and the like and the multi-layer conductor wiring, are partly removed only on each layer conductor wiring 3, 3' whereby the thickness of the insulating films remaining on each layer conductor wirings 3', 3 are made predetermined ones. Then, in the whole surface of the semiconductor integrated circuit substrate, only its insulating films perpendicular to the substrate surface are removed by anisotropic etching to expose the surfaces of the each layer conductor wirings 3', 3. The surfaces of the conductor wirings 3', 3 are analyzed by an electron beam tester using a stroboscopic scanning electron microscope. For example, partial removal of the insulating films 4', 4 are performed by an FIB(focused ion beam) apparatus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for analyzing failures in semiconductor devices, and more particularly to a method for easily analyzing failures in semiconductor devices using an electron beam tester.

[Conventional technology]

Conventionally, failure analysis of this type of semiconductor integrated circuit has been carried out as shown in Figure 2 (
Insulation 11118' for passivation as shown in a)
and observe the potential contrast image or internal waveform using an electron beam tester without removing the insulating films 8 and 8' between the conductor wirings 7 and 7' at all, or observe the potential contrast image or internal waveform as shown in FIG. 2(b).
As shown in Figure 2, similar observations were made after removing the insulating films 8 and 8' between the eyebrows and passivation by etching.[Problem to be Solved by the Invention] case,
First, the method that does not remove the insulating film has the disadvantage that it is not possible to distinguish the potential contrast when the absolute value of the potential that you want to observe with an electron beam tester is small; When a silicon nitride film is used as a silicon nitride film, isotropic plasma etching or the like is used, but as shown in part S in Fig. 2(b),
There is a drawback that the silicon nitride film between the lower layer and the upper layer conductor wiring is removed, resulting in a short circuit between the lower layer conductor wiring and the upper layer conductor wiring.

[Means to solve the problem]

A failure analysis method for a semiconductor device according to the present invention includes: - In a semiconductor integrated circuit having a diffusion region such as a semiconductor element and a multilayer conductor wiring on a main surface, an insulating film for passivation on the semiconductor integrated circuit and a gap between the eyebrows of the multilayer conductor wiring. a step of partially removing the insulating film only on the conductor wiring of each layer so that the thickness of the insulating film remaining on the conductor wiring of each layer is uniform; and a step of removing the entire surface of the semiconductor integrated circuit board. The insulating film is removed only in the direction perpendicular to the substrate surface by directional etching.
The process includes a step of exposing the entire surface of the conductor wiring in each layer, and a step of performing failure analysis on the surface of the conductor wiring in each layer using an electron beam tester using a strobe SEM, and removing an insulating film on the conductor wiring in each layer. FIB (Focused)
The method includes etching the entire surface of the substrate using an RIE (reactive ion etching) device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views showing an embodiment of the present invention in the order of steps, and this embodiment is applied to a method for failure analysis of a silicon semiconductor integrated circuit having 2N wiring using an electron beam tester. .

First, a silicon oxide film 2 is formed on an n-type silicon substrate 1 as shown in FIG. When analyzing a semiconductor integrated circuit formed using silicon nitride films 4 and 4' as shown in FIG.
), we first want to perform failure analysis using FIB (Focused Ion Beam).The thickness of the silicon nitride film 4' on the single-layer aluminum wiring 3' and the double-layer aluminum wiring 3 is made to be the same. Select the FIB etching conditions.

Next, as shown in Figure (c), the silicon nitride film slightly remaining on the first layer aluminum wiring 3' and the second layer aluminum wiring 3 is etched using RIE (reactive ion etching). By anisotropically etching, the result is as shown in FIG. 2(d).

In this way, the surfaces of the single-layer aluminum wiring 3' and the double-layer aluminum wiring 3 are exposed where failure analysis is desired. At this time, the entire surface of the substrate is also slightly etched by RIE.

Then, as shown in FIG. 3(d), an electron beam using a strobe device is periodically irradiated onto the aluminum wirings 3' and 3 of the first and second layers to operate the integrated circuit at the same time. The potential contrast image and internal potential waveform are observed using the strobe SEM principle of synchronizing with electron beam irradiation.

As for the potential difference, a potential contrast image with a small potential of 0.25 V or less can be observed.

In this manner, failure analysis is performed using an electron beam tester.

〔Effect of the invention〕

As explained above, the present invention provides a F
The insulating film that was removed by IB (focused ion beam) etching and remained slightly with the same thickness on the conductor wiring of each layer was completely removed by RIE (reactive ion etching), and each of the above layers was removed. Using an electron beam tester using a strobe SEM to measure the surface of conductor wiring using the potential contrast method and waveform method, very small potential differences,
For example, a potential difference of 0.25V can be easily observed, which has the effect of enabling failure analysis.

[Brief explanation of the drawing]

Figures 1 (a) to (d) are cross-sectional views showing the failure analysis method of the present invention in the order of steps, and Figures 2 (a) to <b> are cross-sectional views for explaining problems in the conventional manufacturing method. be. 1... N-type silicon substrate, 2... Silicon oxide film,
3... Second layer aluminum interconnection, 3'... Second layer aluminum interconnection, 4... Interlayer silicon nitride film, 4'...
... Passivation silicon nitride film, 5... Semiconductor substrate, 6,8.8'... Insulating film, 7.7'... Conductor wiring.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a diffusion region such as a semiconductor element and a multilayer conductor wiring on one main surface, an insulating film for passivation on the semiconductor integrated circuit and an insulating film between layers of the multilayer conductor wiring. Partially removed only on the conductor wiring of each layer,
A step of making the thickness of the insulating film left on the conductor wiring of each layer constant, and removing the insulating film only in the direction perpendicular to the substrate surface by anisotropic etching the entire surface of the semiconductor integrated circuit board. and a step of exposing the entire surface of the conductor wiring in each layer, and performing a failure analysis on the surface of the conductor wiring in each layer using an electron beam tester using a strobe scanning electron microscope. Equipment failure analysis method. 2. Etching and removing the insulating film on the conductor wiring of each layer using a FIB (focused ion beam) device,
2. A failure analysis method for a semiconductor device according to claim 1, further comprising performing anisotropic etching on the entire surface of the substrate using an RIE (reactive ion etching) device.