JPH02265090A - Memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory device that allows a memory circuit to be initialized at high speed.

Conventional technologyAs the density of integrated circuits increases, random access
The storage areas of various storage devices, including memory (hereinafter referred to as RAM), are becoming larger. A conventional storage device will be explained below.

FIG. 2 shows a conventional integrated circuit. In Figure 2, 10
is an input, 11 is a decoder, 12 is a plurality of addresses, 13
4 is a data input, and 15 is a write control input (hereinafter referred to as WE).

Next, the operation of the conventional integrated circuit configured as described above will be explained.

When address data is input to the input 10, the address data is decoded by the decoder 11 and one of the plural addresses 12 becomes valid, and the memory circuit 13
One of the many storage areas is selected. At this time, by setting data in the data input 14 and validating the WE 15, the data is written to the selected storage area.

Problems to be Solved by the Invention In recent years, as micro processors have become more sophisticated, high-speed calculations have been performed using data stored in storage devices. Before performing such calculations,
It is necessary to initialize the storage device. however,
In the conventional configuration described above, when there are N storage areas, it is necessary to write data N times. Today's storage devices with large storage areas have the disadvantage of requiring a large amount of time. The present invention solves the above-mentioned conventional problems, and aims to provide a storage device that can be initialized by writing only once.

Means for Solving the Problems To achieve this object, the storage device of the present invention has means for validating all of a plurality of addresses.

Effect: Since all storage areas can be selected by this means, the storage device can be initialized by writing once.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention. In FIG. 1, ■ is an input, 2 is a decoder, 3 is a plurality of addresses, 1.4 is a control input, 5 is a gate, 6 is a plurality of addresses, 2.7 is a storage circuit, 8
9 is data input, and 9 is writing control human power (hereinafter referred to as WE).

Next, the operation of the storage device configured as described above will be explained.

When address data is input to input 1, decoder 2
The address data is decoded and one of the plurality of addresses becomes valid. When the control power 4 is disabled, the gate 5 operates as a transfer gate, and the contents of the first of the plural addresses are transmitted as is to the second of the plural addresses, and one of the many storage areas of the memory circuit 7 is selected. . At this time, by setting data in the data input 8 and validating the WB2, the data is written to the selected storage area.

When control power 4 is valid, all addresses 2 are valid, regardless of the status of 1 of the multiple addresses.
All storage areas in the storage circuit 7 are selected. At this time, data can be written to all storage areas by setting 9 data to input 8 and enabling WB2.

As described above, according to the present embodiment, by providing the gate 5 between the decoder 2 and the memory circuit 7, all of the plurality of addresses can be validated, and the memory can be stored by writing - degrees. Device initialization can be performed.

Effects of the Invention According to the present invention, by providing means for validating all of a plurality of addresses, it is possible to initialize a storage device with -degree writing. This minimizes the time spent on initialization, which is highly effective when high-speed calculations such as real-time calculations that require completion within a fixed time are required.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional storage device. 2...Decoder, 5...Gate, 7.
...Memory circuit. Figure 1 Figure 2

Claims (1)

[Claims] means for validating one address from a plurality of addresses; means for validating all of the plurality of addresses;
a storage device for writing data into a storage area selected by the valid address.