JPH04237346A - Microprocessor system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a microprocessor system consisting of a microprocessor, ROM, and RAM used for local control, etc. In particular, the present invention relates to a microprocessor system that is used for local control, etc. This invention relates to a small scale microprocessor system with port RAM.

In microprocessor systems, especially local control systems, like other circuits,
Since there is a trend toward smaller size and lower cost, there is a need for a structure that can be easily reduced in size.

0003

5 is a block diagram showing the configuration of a conventional microprocessor system. In the figure, 1 is a microprocessor, 2 is a ROM, 3A is a RAM for work during program execution, and 4A is an operational RAM. Looks like a register I
A 2-port RAM that plays the role of /O control, 5A is an address decoder. This system interfaces with the outside via a 2-port RAM that plays the role of I/O control for a 4A register image.

0004

[Problems to be Solved by the Invention] In the conventional microprocessor system shown in FIG. 5, when the amount of work RAM 3A used is small, the capacity of the work RAM is reduced to achieve miniaturization and cost reduction. Was. However, since two RAMs are used, the work RAM 3A and the 2-port RAM 4A which plays the role of I/O control, there is a problem in that the circuit scale of the system increases. An object of the present invention is to realize a microprocessor system with a small circuit scale without using the conventional work RAM 3A.

[0005]

[Means for Solving the Problems] This purpose is to solve the problem by referring to the principle diagram of FIG. 1 showing the basic configuration of the present invention. This is achieved by the present invention, which also serves as the RAM 3A. In the figure, 1 is a microprocessor, 2 is a ROM, 3 is a work RAM and a 2-port RAM that plays the role of I/O control, and 4 is an address decoder.

[0006] A circuit 5 is added that calculates the logical sum of the chip select (CS) from the microprocessor 1 and the I/O request (I/O REQ), and the output of this circuit is input to the enable terminal EN of the address decoder 4. When the microprocessor 1 accesses the work memory and I/O, the output of the address decoder is used as an address to read and write to the same two-port RAM 3 for access.

[0007]

[Operation] The present invention uses a 2-port RAM having a capacity equal to the sum of the work area required by the microprocessor 1 and the I/O control area as a register.
3, so only one RAM is required. Therefore, the circuit size of the microprocessor system can be reduced. In the conventional example, as shown in Figure 3, the work memory area and I/O
The I/O area for control was physically and logically separate from the control I/O area, but in the present invention, as shown in Fig. 4, it is logically separate as before, but it is physically the same area. Therefore, as shown in Figure 1, the microprocessor's chip select CS and I
/O request I/O REQ The output of the circuit 5 which takes the logical sum with the I/O
By inputting and decoding N, the need for the address of the memory area of the decoder output and the address of the I/O control area to be placed at different locations is satisfied.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a block diagram of a microprocessor system according to an embodiment of the present invention. In the figure, 1 is a microprocessor, 2 is a ROM, 3 is a 2-port RAM, 4 is an address decoder, and 5 is an OR circuit, which is an AND gate with a negative input. In this example, 2-port RAM
3 provides a memory area for the microprocessor 1 to work with 16-bit data, and also serves as I/O control for the 8-bit data register image, and communicates with the outside via the 2-port RAM 3. Take the interface. According to this embodiment, the RAM used is a 2-port RA
Since only one M3 is required, the circuit scale of the microprocessor system can be made smaller than before, and since the number of memory devices used is small, the address decoder can also be made small.

[0009]

[Effects of the Invention] As explained above, according to the present invention, a two-port RAM that serves as a work RAM during program execution and a RAM for register image I/O control is provided.
Since these are combined into one RAM, the number of memory devices is reduced, the burden on the address decoder is reduced, and the effect of reducing the size and cost of the microprocessor system circuit is achieved.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the basic configuration of the microprocessor system of the present invention.

FIG. 2 is a block diagram of a microprocessor system according to an embodiment of the present invention;

[Figure 3] Diagram of logical memory area and physical area in conventional example,

FIG. 4 Diagram of logical memory area and physical area in the embodiment of the present invention,

FIG. 5 is a block diagram of a conventional microprocessor system.

[Explanation of symbols]

1 is microprocessor, 2 is ROM, 3 is 2 port R
AM, 4 is address data, and 5 is an OR circuit.

Claims (1)

[Claims] [Claim 1] Microprocessor 1 and ROM 2
In a microprocessor system that controls external I/O, the address and I/O control signal (I/OREQ) from the microprocessor is
One 2-port RAM 3 is provided with a circuit 5 that performs the logical sum of the two-port RAM 3 and performs the role of I/O control of the register image by decoding the output of the circuit and using it as the data address of the 2-port RAM. 1
A microprocessor system that also serves as a work RAM when executing a program.