JPH02265323A - logic circuit - Google Patents

Abstract

PURPOSE:To reduce the leading delay time of an output signal by connecting an output terminal and a base of a phase split transistor(TR) when a potential of the output terminal lead between both output TRs is moved negative more than the L level. CONSTITUTION:A connection means 49 is provided between an output terminal 2 of an output circuit 30 and a base of a phase split TR T3. The connection means 40 acts like connecting the base of the T3 and the output terminal 2 when the potential at the output terminal 2 is moved negative more than the L level. That is, the connection means 40 connects the base of the T3 and the output terminal 2 at an undershoot when the level at the output terminal 2 is moved negative more than the L level. Thus, the potential of the output terminal 2 is clamped to a potential corresponding to the base potential of the T3, and the potential fluctuation of the output signal V0 attended with undershoot and the delay time at the leading of the output signal V0 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit, and particularly to a logic circuit that can suppress undershoot of an output signal.

In recent years, various types of logic ICs, such as TTL type, 5TTL type logic, or CMO3 type O3 type IC, are becoming faster and faster. Furthermore, there is a remarkable trend towards multi-bins due to the multifunctionality of ICs.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional logic circuit constituting a logic IC, and is a TTL type logic circuit. In this figure, logic circuit 1 has an H-level power supply line (hereinafter referred to as Vcc
) and the L-level power supply line (hereinafter referred to as GND), the H-level output transistors T1m and T1 are connected in a totem pole.
An output comprising o and L level output transistors Tz, an output terminal 2 drawn out from a connection point between these two output transistors, and a phase split transistor T that conducts one of the two output transistors in accordance with an input signal Vt. It has a circuit 3, and this output circuit 3 is T
o, output signal ■ when Tlb is conductive. is set to H level, and vo is set to L level when T2 becomes conductive. In addition, T, ~T6 are transistors, R1-R8 are resistors, DI""03 is a Schottky barrier diode,
4 is an input terminal.

[Problem to be solved by the invention]

However, in such conventional logic circuits,
While the state of the output signal v0 is at the L level, for some reason the state of the output signal v0 changes more deeply to the negative side than the L level (usually deeper than Ov), causing a so-called undershoot. was there. Possible causes of this include, for example, the influence of switching operations of other gates, reflections from the load side, or crosstalk.

And while such undershoot occurs, the output signal ■. When an attempt is made to change the state from the L level to the H level (hereinafter referred to as rise), there is a problem in that the rise time is significantly delayed.

That is, in FIG. 5, when the state of the input signal Vi changes from H level to L level, the output signal v0
Normally, the rise changes after a slight delay time t2 as shown by the waveform, but if an undershoot occurs, the delay time t changes as shown by the waveform ■.
l (t, > t,).

This is caused by the Schottky barrier diode SBD between the base and collector of the L level output transistor T, due to the undershoot of vo (fluctuation to the negative side of Ov).
(See FIG. 4) is forward biased and the emitter current of the phase split transistor T is drawn through the SBD, resulting in a delay in the time for the phase split transistor T3 to change from on to off.

The present invention was made in view of these problems, and
The purpose is to suppress undershoot of the output signal and shorten the rise delay time of the output signal.

[Means to solve the problem]

In order to achieve the above object, the logic circuit according to the present invention has H
An H level output transistor and an L level output transistor are connected in a totem pole between a level power line and an L level power line, and a phase split transistor makes one of the two output transistors conductive depending on the input signal applied to the base. In the logic circuit, when the potential of the output terminal drawn from between the two output transistors changes to the negative side from the L level, the output terminal and the base of the phase split transistor are connected. It is configured by providing a connection means.

[Effect]

In the present invention, when an undershoot occurs in the output signal, the connection means connects the output terminal and the base of the phase split transistor, the base current of the phase split transistor flows to the output terminal, and the phase split transistor is turned off. When the phase split transistor turns off, the H level output transistor turns on and the potential of the output terminal is pulled back to the positive side of the L level.Then, when the potential of the output terminal becomes more positive than the L level. Since the connection between the output terminal and the base of the phase split transistor becomes disconnected, the phase split transistor becomes "on" again, and the potential of the output terminal becomes L level.

Therefore, the time during which undershoot appears is shortened.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing an embodiment of a logic circuit according to the present invention. Note that the same parts as in FIG. 4 are given the same numbers and their explanations will be omitted.

FIG. 1 is a principle block diagram of one embodiment, and is a diagram showing an output circuit 30 constituting a logic circuit. In FIG. 1, a connecting means 40 is provided between the output terminal 2 of the output circuit 30 and the base of T3, and this connecting means 40 allows the potential of the output terminal 2 to fluctuate to the negative side from the L level. When you do,
It functions to connect between the output terminal 2 and the base of T3.

That is, according to such a configuration, when undershoot occurs when the potential of the output terminal 2 changes to the negative side from the L level, the connection means 40 connects the base of T and the output terminal 2. The potential of the output terminal 2 is clamped to a potential corresponding to the base potential of T, which makes it possible to suppress potential fluctuations in the output signal v0 due to undershoot, and shorten the delay time when the output signal v0 rises. .

FIG. 2 shows an output circuit 3 including a connection means 40 having a specific configuration.
0 is a configuration diagram. In this figure, the connecting means 40 includes a transistor T and a resistor R7.

The transistor Ts has its collector connected to the base of T, its emitter connected to the collector of T2 (ie, output terminal 2), and its base connected to GND via a resistor R1.

According to such a configuration, when an undershoot as shown in FIG. 3 occurs in the output signal v0, the output signal v0
The potential of is a potential (VCLMP) that is lower than the GND potential (OV) by the base-emitter potential (Vl!1) of T.
As a result, the output signal is clamped to■. -VCL
It can be raised to the potential of □. Therefore, undershoot can be suppressed and the output signal ■. It is possible to shorten the delay time when the rising edge (L→H) changes.

〔Effect of the invention〕

According to the present invention, undershoot of the output signal can be suppressed, and the rise delay time of the output signal can be shortened.

FIG. 1 is a diagram of its principle configuration, FIG. 2 is a detailed diagram of its configuration, and FIG. 3 is a timing chart showing changes in the rise of its output signal.

4.5 is a diagram showing a conventional logic circuit, FIG. 4 is a configuration diagram thereof, and FIG. 5 is a timing chart showing changes in the rise of its output signal.

To, T1. ...H level output transistor,
Tz...L level output transistor, T...
...Phase split transistor, 2...
...Output terminal, 40... Connection means.

[Brief explanation of drawings]

1 to 3 are diagrams showing one embodiment of the logic circuit according to the present invention, and have the following structure: T: t: Level output transistor T:: Phase split transistor 2: Output terminal 40: Connecting means 1 Embodiment principle structure Figure 1: Timing chart showing changes in the rise of the output signal Figure T3: Phase blit transistor 40: Specific configuration diagram of an embodiment of connection means

Claims (1)

[Claims] An H level output transistor and an L level output transistor are connected in a totem pole between an H level power line and an L level power line, and both output transistors are connected in accordance with an input signal applied to their bases. In a logic circuit comprising a phase split transistor, one of which is made conductive, when the potential of the output terminal drawn from between the two output transistors changes to the negative side from the L level, the output terminal and the phase split transistor are connected to each other. A logic circuit characterized in that it is provided with connection means for connecting to a base.