JPH02266538A - Manufacturing apparatus for semiconductor device - Google Patents
Manufacturing apparatus for semiconductor deviceInfo
- Publication number
- JPH02266538A JPH02266538A JP8762889A JP8762889A JPH02266538A JP H02266538 A JPH02266538 A JP H02266538A JP 8762889 A JP8762889 A JP 8762889A JP 8762889 A JP8762889 A JP 8762889A JP H02266538 A JPH02266538 A JP H02266538A
- Authority
- JP
- Japan
- Prior art keywords
- defect
- marks
- defects
- pellets
- assembly process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 230000007547 defect Effects 0.000 claims abstract description 42
- 239000008188 pellet Substances 0.000 claims abstract description 16
- 230000002950 deficient Effects 0.000 claims abstract description 13
- 238000000465 moulding Methods 0.000 claims abstract description 9
- 238000005452 bending Methods 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 29
- 238000007689 inspection Methods 0.000 abstract description 14
- 239000003550 marker Substances 0.000 abstract 4
- 238000001514 detection method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011143 downstream manufacturing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明は、半導体組立工程において発生した組立不良
を検査工程前に自動的に除去できる半導体装置の製造装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to a semiconductor device manufacturing apparatus that can automatically remove assembly defects that occur during a semiconductor assembly process before an inspection process.
従来の技術
半導体組立工程においてリードフレームに対して、ペレ
ットマウント時に発生するマウント位置の規定外れ、ペ
レット外れ、不良印付ペレットのマウント等の組立不良
とワイヤーボンディングに発生するワイヤーボンディン
グ位置の規定外れ、パターン認識が不可能なペレット、
ワイヤー倒れ等の組立不良及びモールド時に発生する樹
脂の未充填、ボイド等の組立不良は、リードフレーム状
であるための各工程で取り除（ことができず、モールデ
ィング後、外観で判定できるもののみ、リードカット・
ベンド加工後、人為的に除去をしているが、ペレットマ
ウント・ワイヤーボンディング不良は、上記方法の判定
はできず、後工程の電気的検査まで良品として扱ってい
た。Conventional technology In the semiconductor assembly process, assembly defects such as unspecified mounting position when mounting pellets, pellets coming off, and mounting of defective pellets when mounting pellets on lead frames, and unspecified wire bonding positions that occur during wire bonding. Pellets with no pattern recognition,
Assembly defects such as falling wires, unfilled resin, and voids that occur during molding cannot be removed during each process due to the lead frame shape, and can only be determined by the appearance after molding. , lead cut・
After the bending process, they were removed manually, but defects in pellet mount and wire bonding could not be determined using the above method, and were treated as non-defective until electrical inspection in the post-process.
発明が解決しようとする課題
しかしながら、上記従来の構成では、上記検査以前の不
良まで検査をしていたので、検査コストが高くなるとい
う問題があった。Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, since defects even before the above-mentioned inspection were inspected, there was a problem that the inspection cost increased.
本発明は上記従来の問題を解決するもので、上記不良を
検査以前の工程で自動除去をする半導体製造ラインを提
供することを目的とする。The present invention solves the above-mentioned conventional problems, and aims to provide a semiconductor manufacturing line that automatically removes the above-mentioned defects in a process before inspection.
課題を解決するための手段
この目的を達成するために、本発明の半導体製造ライン
は、ペレットマウント・ワイヤーボンディング・モール
ディング工程の各工程に不良検出装置と不良マーキング
装置とを備え、リードカット・ベンド工程に上記不良マ
ークの検出装置と不良除去装置とを備えている。Means for Solving the Problems In order to achieve this object, the semiconductor manufacturing line of the present invention is equipped with a defect detection device and a defect marking device in each step of the pellet mounting, wire bonding, and molding processes, and is equipped with a defect detection device and a defect marking device for lead cutting, bending, and The process is equipped with the defect mark detection device and defect removal device.
作用
この構成によって、組立工程の不良が、後工程の電気的
検査以前に除去されるために、検査コストを下げること
ができる。Effect: With this configuration, defects in the assembly process are removed before electrical inspection in the post-process, so inspection costs can be reduced.
実施例
以下本発明の一実施例について、図面を参照しながら説
明する。第１図は本発明の一実施例における半導体装置
の製造装置のライン構成図を示すものである。第１図に
おいて、１はペレットマウント装置、２は不良検出装置
、３は不良マーキング装置、４はワイヤーボンディング
装置、５はモールディング装置、６はリードカット・ベ
ンド装置、７は不良マーク検出装置、８は不良除去装置
であり、第２図は本発明の一実施例におけるリードフレ
ームへの不良マーク位置を示すものである。第２図にお
いて、９はリードフレーム、１０は不良マーク、１１は
モールディング外形線を示すものである。EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 shows a line configuration diagram of a semiconductor device manufacturing apparatus in an embodiment of the present invention. In FIG. 1, 1 is a pellet mounting device, 2 is a defect detection device, 3 is a defect marking device, 4 is a wire bonding device, 5 is a molding device, 6 is a lead cutting/bending device, 7 is a defect mark detection device, 8 2 is a defect removal device, and FIG. 2 shows the position of a defective mark on a lead frame in an embodiment of the present invention. In FIG. 2, 9 is a lead frame, 10 is a defective mark, and 11 is a molding outline.
以上のように構成された本実施例の半導体製造ラインの
動作を説明する。The operation of the semiconductor manufacturing line of this embodiment configured as described above will be explained.
まず、第１図のペレットマウント装置１で発生した組立
不良は、不良検出装置２より検出され、第２図のモール
ディング外形線１１の斜線部課外の箇所に不良マーク１
０を第１図の不良マーキング装置３により印される。ワ
イヤーボンディング装置４及びモールディング装置５も
同様に不良マーク１０が印され、次工程のリードカット
・ベンド装Ｍ６の不良マーク検出装置７により、上記の
組立不良は検出され、不良除去装置８により、リードフ
レーム９から分離される。First, an assembly defect occurring in the pellet mount device 1 shown in FIG.
0 is marked by the defect marking device 3 of FIG. A defective mark 10 is similarly marked on the wire bonding device 4 and the molding device 5, and the defective mark detection device 7 of the lead cutting/bending device M6 in the next process detects the assembly defect, and the defect removing device 8 removes the lead. It is separated from the frame 9.
以上の様に本実施例によれば、ペレットマウント・ワイ
ヤーボンディング工程の各工程に不良検出装置と不良マ
ーキング装置とを備え、リードカット・ベンド工程に不
良検出装置と不良マーキング装置とを偏えたことにより
、後工程の電気的検査コストの低減をはかることができ
る。As described above, according to this embodiment, a defect detection device and a defect marking device are provided in each process of the pellet mounting and wire bonding processes, and the defect detection device and defect marking device are biased to the lead cutting and bending processes. Therefore, it is possible to reduce the electrical inspection cost in the post-process.
発明の効果
本発明によれば、半導体製造ラインの組立工程に不良検
出装置と不良マーキング装置及び組立最終工程に不良マ
ーク検出装置と不良除去装置を設けることにより、組立
工程の不良が後工程の電気的検査工程前で除去され、電
気的検査コストの低減をはかることができる優れた半導
体装置の製造装置をつ（り上げることができる。Effects of the Invention According to the present invention, by providing a defect detection device and a defect marking device in the assembly process of a semiconductor manufacturing line, and a defect mark detection device and a defect removal device in the final assembly process, defects in the assembly process are prevented from occurring in the downstream process. It is possible to create an excellent semiconductor device manufacturing apparatus that can be removed before the electrical inspection process and reduce electrical inspection costs.
第１図は本発明の一実施例における半導体製造ラインの
ライン構成図、第２図は本発明の一実施例におけるリー
ドフレームに対する不良マーキング位置を示す平面図で
ある。
１・・・・・・ペレットマウント装置、２・・・・・・
不良検出装置、３・・・・・・不良マーキング装置、４
・・・・・・ワイヤボンディング装置、５・・・・・・
モールディング装置、６・・・・・・リードカット・ベ
ンド装置、７・・・・・・不良マーク検出装置、８・・
・・・・不良除去装置。FIG. 1 is a line configuration diagram of a semiconductor manufacturing line according to an embodiment of the present invention, and FIG. 2 is a plan view showing defective marking positions on a lead frame according to an embodiment of the present invention. 1... Pellet mount device, 2...
Defect detection device, 3... Defect marking device, 4
...Wire bonding equipment, 5...
Molding device, 6... Lead cutting/bending device, 7... Defective mark detection device, 8...
...Defect removal device.
Claims (1)
ントするとともに根を検出し、マーキングするペレット
マウント装置と、上記マウントされたペレットの電極と
上記リードフレームのリードとを接続するとともに不良
を検出し、マーキングするワイヤーボンディング装置と
、上記ペレットとワイヤーを保護する樹脂によるととも
に不良を検出し、マーキングするモールディング装置と
、不良マークを検出した後上記リードフレームの不要部
分をカッティングし、不良を除去するとともに良品のリ
ード部のペンディングをするリードカット・ベンド装置
を備えたことを特徴とする半導体装置の製造装置。A pellet mount device that mounts semiconductor pellets on a continuous or fixed length lead frame, detects roots, and marks them; and connects the electrodes of the mounted pellets to the leads of the lead frame, detects defects, and marks them. a wire bonding device that uses resin to protect the pellets and wires, and a molding device that detects and marks defects; and after detecting defective marks, cuts unnecessary parts of the lead frame, removes defects, and marks them as good products. A semiconductor device manufacturing device characterized by being equipped with a lead cutting/bending device for pending lead portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8762889A JPH02266538A (en) | 1989-04-06 | 1989-04-06 | Manufacturing apparatus for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8762889A JPH02266538A (en) | 1989-04-06 | 1989-04-06 | Manufacturing apparatus for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02266538A true JPH02266538A (en) | 1990-10-31 |
Family
ID=13920242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8762889A Pending JPH02266538A (en) | 1989-04-06 | 1989-04-06 | Manufacturing apparatus for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02266538A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05304177A (en) * | 1992-04-28 | 1993-11-16 | Nec Yamagata Ltd | Assembly system of semiconductor device |
| KR100363736B1 (en) * | 2000-02-22 | 2002-12-06 | 동양반도체장비 주식회사 | Reject material eject unit of marking apparatus for semiconductor package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134057A (en) * | 1984-12-05 | 1986-06-21 | Oki Electric Ind Co Ltd | Cmos type ic device |
| JPS6225641A (en) * | 1985-07-26 | 1987-02-03 | 積水化学工業株式会社 | Panel |
-
1989
- 1989-04-06 JP JP8762889A patent/JPH02266538A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61134057A (en) * | 1984-12-05 | 1986-06-21 | Oki Electric Ind Co Ltd | Cmos type ic device |
| JPS6225641A (en) * | 1985-07-26 | 1987-02-03 | 積水化学工業株式会社 | Panel |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05304177A (en) * | 1992-04-28 | 1993-11-16 | Nec Yamagata Ltd | Assembly system of semiconductor device |
| KR100363736B1 (en) * | 2000-02-22 | 2002-12-06 | 동양반도체장비 주식회사 | Reject material eject unit of marking apparatus for semiconductor package |
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