JPH02266965A - Printer - Google Patents

Abstract

PURPOSE:To contrive to accelerate printing without accompanying the capacity increase of a picture memory by writing only the effective block including effective data in said picture memory through making an exception of a null block composed of only blank data. CONSTITUTION:When the word address of a virtual page is generated from an address generator 43, a picture memory write controller 42 reads data of said word address in word units from said virtual page 61. On the basis of a decision result obtained in a data decision part 41, then, data of one word of said word address are written in a picture memory 30 not when said data are blank data but when they are effective data. Further, when the decision result of said data being effective data is inputted from the data decision part 41 to the picture memory write controller 42 and the decision result of a virtual block address generated by the address generator 43 differing from that generated just before is inputted to said picture memory write controller 42, said controller 42 refers to the address conversion memory 44a of an address converter 44.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a printing device that stores print data in an image memory and prints on paper while reading the data.

(Prior Art) Various devices are known for printing print data created by a host control device such as a computer or a word processor onto paper, such as electrophotographic printers, thermal printers, and wire dot printers. It is being

FIG. 2 shows a block diagram of a printing apparatus that employs a conventional electrophotographic method.

In this device, a processor 4, a program memory 5, a working memory 6, a font memory 7, an image memory 8, and a print engine interface 9 are connected to a system bus 3 connected to a host control device 1 via an interface 2. It is of composition. A print engine 10 is connected to the print engine interface 9.

The host device l is a device such as a computer, word processor, or image reading device that creates print data. The interface 2 is a known circuit composed of a so-called R3232C interface, a parallel interface, or the like. The processor 4 is a circuit that controls the entire printing apparatus, and its execution program is stored in the program memory 5. The working memory 6 is a memory for storing and managing data transmitted and received by the interface 2. The font memory 7 is connected to the upper control device 1.
This is a memory that converts character codes and other codes sent from the printer into font data for printing.

The image memory 8 is composed of a random access memory that stores, for example, one page of print data that has been edited and turned into an image.

The print engine IO is a device that prints on printing paper based on the printing data stored in the image memory 8, and includes a paper transport system, an electrophotographic process, and the like. The print engine interface 9 reads print data 9a from the image memory 8 and transfers it to the print engine 10 according to instructions from the processor 4, or accepts a print control signal 9b output from the print engine 10 and sends it to the processor 4, etc. This is an interface circuit for transmitting data.

The above-described printing device temporarily stores control commands, character codes, graphic commands, bit image data, etc. received from the host control device 1 via the interface 2 in the working memory 6 as needed, and then outputs them to the processor. 4, imaged printing data is created on the image memory 8.

The print data in the image memory 8 created in this way is
It is processed as follows.

FIG. 3 is a conceptual diagram illustrating the operation of reading print output from a conventional image memory.

As shown in the figure, when the read address 8a is input to the image memory 8, each of the rasters ■, ■ in the image memory 8
, ■, ■... are read out in order, and are printed in that order (■.

(■, ■, ■...) A printout 20 is obtained. That is, the data read from the image memory 8 is converted into a bit stream for each raster and sent to the print engine 10 shown in FIG. can get. Note that data is normally read from the image memory 8 not in bits but in words.

FIG. 4 is an explanatory diagram showing more specifically a conventional method of reading out print output from an image memory.

■As shown in the figure, the image memory is for each raster.

. . . are separated in units of one word (for example, 8 bits). The data is sequentially read in word units as (1), (2), (3), etc., and a printout as shown on the right side is obtained.

As can be seen from this figure, there is a complete one-to-one correspondence between the data stored in the image memory 8 and its print output 20. Normally, the image memory 8 has a print output of about one page. 20 is set to the possible memory capacity, and even if the amount of information being printed is very small, one page's worth of print data is always stored in the image memory 8 and then printed. was.

(Problem to be Solved by the Invention) Incidentally, in an electrophotographic printing apparatus, a photosensitive drum having a photosensitive layer formed on its outer periphery is fixed.

While rotating at a high speed, an electrostatic latent image corresponding to the print data is formed on the photoreceptor.The electrostatic latent image is developed using toner, transferred to the paper, and fixed. , such a printing process is carried out in a continuous operation and cannot be interrupted. Therefore, normally, after the printing data has been completely edited in the image memory 8, the conveyance of the paper is started and the printing process is started.

FIG. 5 is an explanatory diagram of the operation of the print engine that executes such a printing process.

In the figure, paper 12 to be printed is stored in trays 11a and 11b. This paper 12 is pulled out by a hopping roller 13a or 13b,
It is transported on the transport path 14.

In front of the conveyance path 14, a photosensitive drum 15 and a writing device 16 for writing an electrostatic latent image on the outer periphery of the photosensitive drum 15 are arranged. This writing device 16 is composed of, for example, a light emitting diode array or a laser head.

In this device, the paper 12 is transported through the transport path 14, and when it reaches the transfer position Wo, the toner on the photosensitive drum 15 is transferred, fixed by a fixing device (not shown), and then discharged. At a point WP on the road, the conveyance is temporarily stopped by a registration roller or the like (not shown), and the conveyance is then resumed at the same time as the writing device 16 starts writing the electrostatic latent image. That is, the photosensitive drum 15
While rotating by J2o (angle α), the paper 12 is conveyed by j2o' and just reaches the transfer position W0.

In order to control such timing, the timing at which printing data is transferred from the image memory 8 to the writing device 16 in FIG.
This is after the hopping roller 13b has conveyed the paper 12 by a distance of 41+4 degrees.

FIG. 6 is a time chart showing the timing of writing data to the image memory and the timing of reading data.

As shown in the figure, when writing starts at time to and writing of the first page print data to the image memory ends at time t, time 1. Then, the hopping roller 13a or 13b shown in FIG. 5 starts conveying the paper 12. Thereafter, after waiting until time ts, reading of the first page print data from the image memory starts from time t3 to time t.
s, the tray 11a shown in FIG.

The paper 12 pulled out from 11b is
It is transported to point Wp. Then, it is transported toward the transfer position We (FIG. 5) at the same timing by registration rollers or the like. In this way, the printing process for the first page is advanced. .

On the other hand, if printing data is alternately written and read from the image memory, the waiting time on the print engine side increases.

Therefore, in order to speed up the processing, reading of the data on the first page is started, and before the reading is finished, writing of the data on the second page is started from time 0 ts to time t3. is the time from the start of reading the first page to securing a certain memory area for writing the data of the second page. Usually, as shown in the figure,
Comparing the time to read data from the image memory and the time to write to the image memory, in the case of writing, time is required for checking the write margin, calculating the write address, accessing the font memory, etc., so the total processing time is slightly shorter. It will be longer.

Considering these points, conventionally, when trying to utilize the image memory to the maximum extent possible, it is necessary to set the operation timing based on the write operation.

FIG. 7 is a timing chart showing the timing of a conventional image memory write operation.

As shown in the figure, each writing operation for one page to the image memory is marked with ■, ■, ■...■, and the waiting time is tXl between each writing operation. It is necessary to provide

This waiting time is the time t1 to t shown in FIG.
This is the time to wait for paper transport and reading of a certain amount of data from the image memory. Therefore, in a printing apparatus in which the memory capacity of the image memory is one page, the timing shown in FIG. 7 is the timing of maximum efficiency, and further speeding up cannot be achieved.

On the other hand, if two pages of image memory are provided, while reading and printing data from one page of image memory, data can be written to another page of image memory. The waiting time t x shown in FIG.
+-t XI can be eliminated.

FIG. 8 is a timing chart showing such a most desirable image memory write operation.

As shown in this figure, printing speed can be increased by increasing the capacity of the image memory. However, increasing the capacity of the image memory causes an increase in the cost of the device.

In particular, as the resolution of printed images increases, a larger capacity image memory is required.
The price difference between these devices and other devices with more features will become larger and larger.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a printing device that can speed up printing without increasing the capacity of the image memory.

(Means for Solving the Problems) A printing device of the present invention includes an image memory that stores print data, a print control unit that writes print data to the image memory, and a print control unit that reads print data from the image memory. and a printing unit that performs printing while printing, and the print control unit divides a virtual page consisting of one page of images virtually set corresponding to print output into a plurality of blocks, and prints the virtual page. When the address of each block in the virtual page is called a virtual block address, the virtual block address of the accessed data is An address determination unit that determines whether the address is the same as or different from the virtual block address of the data accessed immediately before, and based on the determination result of the data determination unit, select only the valid data and write the data to the image memory. an image memory write control unit that associates the virtual block address where the valid data was written with the block address of the image memory where the valid data was written, and an address storing a mapping flag that identifies a valid block containing valid data and a blank block consisting only of blank data, and a page identification flag that identifies a virtual page to which the valid block written in the image memory belongs; A conversion section is provided, and when the image memory write control section accesses the data, based on the determination result of the address determination section, if the virtual block address of the data accessed immediately before is different, the address conversion section , and if the virtual block address of the data accessed immediately before is the same, the address translation result at the time of accessing the data immediately before is used. .

(Function) Even if the device described above has an image memory with a capacity for one page, for example, it is possible to store data for several pages depending on the content of the print data.

First, a virtual page is set on the processor side for each page to be printed. Then, each virtual page is divided into multiple blocks. Among these blocks, blank blocks consisting only of blank data are excluded, and only valid blocks containing valid data are written into the image memory. For virtual pages with many blank spaces, this effective number of blocks will be very small. Therefore, it is possible to store several virtual pages in one page of image memory.

In this way, an address converter is provided to store valid data in a predetermined block of the image memory or to read and print data stored in the image memory.

The printing control section refers to the block addresses and flags stored in the address conversion section, identifies the valid blocks and blank blocks of each virtual page, and determines which virtual page's valid block corresponds to which block address in the image memory. Recognize what is stored.

When reading data, the print control section generates blank data for blank block portions, and only valid data is read from the image memory at a predetermined timing.

Note that when writing valid data to the image memory or continuously outputting valid data or blank data contained in a valid block from the image memory, 9. Before referring to the address translation section, the address determination section compares the virtual block address of the data that is currently being accessed and the virtual block address of the data that was accessed immediately before, and determines whether or not they are the same.

If the two are different, address translation is performed with reference to the address translation unit. Furthermore, if the two are the same, no address translation is performed and the address already in the address translation unit is used to prevent unnecessary address translation.

Thereby, a printout corresponding to the virtual page is obtained.

(Example) Configuration of the device Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of a printing apparatus of the present invention. The overall configuration of this device is similar to that shown in FIG. 2, but in this device, writing and reading of data in the image memory 3o is controlled by a print control section 40 as shown in the figure.

This device includes a block determination unit 41 that receives and receives print data 60, an image memory write control unit 42 that assigns a write address for that data to the image memory 30, and generates an address in word units of data to be accessed. an address generation unit 43 that compares the virtual block address of the data that is currently being accessed with the virtual block address of the data that was accessed immediately before, and an address conversion unit that performs predetermined address conversion, etc. 44, a connection switching circuit 45 for switching the input path of write data to the image memory 30 or the output path of read data, and a printing section 50.

Principle of Operation> Before explaining the detailed operation of this apparatus, first, the principle operation of the apparatus of the present invention will be explained using FIG.

In FIG. 9, this example shows a case where printing of two virtual pages (2) and (3) is requested.

First, the virtual pages ■ and ■ are each divided into a plurality of blocks 62 and 62'. For example, each block has a 128×128 bit configuration. When a virtual page is divided into a plurality of blocks in this manner, each block is classified into a blank block 62' consisting only of blank data and a valid block 62 containing valid data. Then, the print control unit 40 shown in FIG.
Only the valid block 62 containing the valid data of (2) is written. In this way, each virtual page ■,
Although the image (2) is disassembled into pieces, two pages worth of effective blocks 62 can be stored with sufficient margin in the image memory 30 with a capacity for one page.

In this way, after writing the print data to the image memory 30, in order to obtain the print outputs ■ and ■ shown on the right side of FIG. 9, it is necessary to write the first block (coordinates ( 0, 0)) is a blank block 62'', and if it is a blank block, the image memory write control unit 42 of FIG. 1 generates blank data there and directs it to the printing unit 5o. If it is a valid block 62, the data corresponding to the valid block is read from the image memory 30 and output to the printing unit 50.

As a result, it is possible to reproduce the print outputs ■ and print outputs ■ corresponding to the virtual pages ■ and ■.

Also, while printing the virtual page ■ print output ■,
The printing data of the virtual page (2) can be written to the image memory 30 in parallel, and the processing speed can be increased.

<Configuration of Each Block> Returning to FIG. 1 again, the specific configuration of the apparatus of the present invention will be described.

In FIG. 1, printing data 60 is divided into a large number of blocks 62 when viewed from a virtual page 61. As shown in FIG.

When performing a write operation, the data is input to the data determining section 41 and the connection switching circuit 45 in units of one word (for example, 8 bits). The data determining unit 41 is a circuit that determines whether one word of write data is blank data or valid data. That is, the write data and the reference value 41a (data set to the level of blank data) are input to the comparator 41b provided in the data determination section 41. and,
The determination result is input to the image memory write control section each time.

The image memory write control unit 42 is a microprocessor or LS that controls writing of data to the image memory 30.
This circuit is composed of I, etc. Based on the determination result output from the comparator 41b, the image memory write control unit 42 blocks writing of the write data to the image memory 30 when the write data is blank data, and switches the connection when the write data is valid data. The write data input to the image memory 30 is controlled to be written to a predetermined address via the circuit 45.

Therefore, if one block 62 of the virtual page 61 consists entirely of blank data, the corresponding block will never be written to the image memory, whereas even one word of valid data will be written to the image memory. If so, that valid data is written to the image memory, and the block containing that valid data is thereafter treated as a valid block.

The address generation section 43 is a circuit that generates a word address to read data from the virtual page 61 word by word and outputs it to the image memory write control section 42 and the address determination section 8o.

When the address of each block of the virtual page is called a virtual block address, the address determination unit 80 compares the virtual block address of the virtual page 61 output by the address generation unit 43 with the virtual block address output immediately before, This is a circuit that determines whether the two are the same. This virtual block address is the upper bit of the word address, and corresponds to the address of a common part throughout one block.For example, the address space of the virtual page 61 is 2.
It is expressed in 4 bits, with an l block consisting of 128 x 128 bits, and 1 word having 8 bits. When the in-block address of each word is assigned to the lower bits,
Eleven bits are required for the intra-block address.

Therefore, of the total 24 bits, the upper 13 bits become the block address representing the block. That is, the comparator 80b provided in the address determination section 80 receives the virtual block address generated by the address generation section 43 and the immediately preceding virtual block address stored in the register 80a. The determination result is input to the image memory write control section 42.

The address conversion unit 44 associates a mapping flag T that identifies whether each block is a valid block or a blank block in the order of the virtual block addresses of the virtual page 61 with a block address RM of the image memory 30 into which each valid block is written. It has an address conversion memory 44a for. The address translation memory 44a has a capacity capable of storing flags and the like for all virtual blocks of a plurality of virtual pages. In addition to this, the address conversion unit 44 sets a page identification flag P+-P for identifying which virtual page's effective block is written in the block address in the order of the block addresses of the image memory 30.
Free block instruction memory 44b for storing x
It is equipped with

The image memory write control section 42 includes the address determination section 8
Based on the judgment result of 0, if the virtual block address of the data to be written now is the same as the virtual block address of the data written immediately before, the address already stored in a register (not shown) is The converted address is used with reference to the conversion unit 44. The lower bits except for the block address do not need to be converted, so they are used as they are. Further, if the virtual block address is different from the virtual block address of the data written immediately before, the data of each virtual page is written into the image memory 3o in the manner shown in FIG. 9 while referring to the address conversion unit 44. Also, in the case of printing,
The data is read out to the printing unit 50 via the connection switching circuit 45.

The printing unit 5o is a print engine having the same mechanism as that described in FIG.

Operation of the device> The printing apparatus of the present invention having the above configuration operates as follows.

First, when a word address of a virtual page is generated from the address generation section 43, the image memory write control section 42
Data at this word address is read from the virtual page 61 in word units (for example, in 8-bit units). Next, based on the determination result obtained in the data determination section 41,
If the word data is blank data, the image memory 30
If the data is valid, it is written to the image memory 30. At this time, a fixed word address is generated from the address generation section 43, and the fixed write data is input to the data determination section 41. A strobe signal indicating that the address is being read is output from the address generating section 43. In response to this, the image memory write control unit 42 outputs an acknowledge signal to the address generation unit 43 each time the data access process is completed, indicating that the next word address and write data can be accepted. When the data determining unit 41 is determining valid data,
The address determination unit 80 determines whether the virtual block address of the data accessed immediately before and the virtual block address of the data currently accessed are the same or different.

A determination result that the read data is valid data is input from the data determination unit 41 to the image memory write control unit 42, and the virtual block address generated by the address generation unit 43 is the virtual block address generated immediately before. When the determination result that the image memory write control unit 42 is different from the above is input to the image memory write control unit 42, the image memory write control unit 42
The address translation memory 44a of the address translation unit 44 is referred to.

Further, the determination result that the read data is valid data is input from the data determination unit 41 to the image memory write control unit 42, and the virtual block address generated by the address generation unit 43 is the virtual block address generated immediately before. When the determination result that the block address is the same as the block address is input to the image memory write control unit 42, the image memory write control unit 42 does not refer to the address conversion memory 44a of the address conversion unit 44, and instead of referring to the address conversion memory 44a of the address conversion unit 44, the image memory write control unit 42 The converted block address obtained by referring to the address conversion memory 44a of the address conversion unit 44 during the previous access and stored in the 1/register (not shown) is used.

Address Conversion Unit> FIG. 1O shows a detailed operation explanatory diagram of the address conversion unit.

This address conversion memory 44a stores a mapping flag T indicating whether the block containing the currently read data is a blank block or a valid block, and the block address RM of the image memory 30 into which the block is written. ing. When storing the first word of data constituting the blank block or valid block in the image memory 30, the mapping flag has an initial value of zero, and the block address R of the image memory 30
M is also undecided. As described above, each block is written one word at a time, and when valid data is input to the data determination section 41, the mapping flag is set to 1. At that point, a predetermined block address of the image memory 30 is written into the block address RM of the image memory 30 of the address conversion section 44, and then data corresponding to that one word is written into the block address of the image memory 30.

All data included in the same virtual block following the one word of data have the same virtual block address. Therefore, based on the output of the address determination section 80, the image memory write control section 42 adds the lower bits of the word address to the block address of the image memory held in the register, and performs write control to the image memory.

On the other hand, when valid data included in a predetermined valid block of the virtual page 61 is written to a predetermined block address of the image memory 30, the free block designation memory 44b of the address conversion unit 44 stores the address of the image memory 30. A page identification flag is written for each block address to identify which virtual page's data is stored. Similar to the mapping flag, this page identification flag has a content of 11 if the page is mapped, and 0 if the page is not mapped.

Therefore, for each block address in the image memory 30, if the page identification flags are all zero, it is known that the block has not been mapped, and if any page identification flag is 1, the block has already been mapped. It can be seen that the block is When determining a block address for writing a new valid block, reference is made to this empty block designation memory 44b.

In this way, when the address generation section 43 in FIG. 1 supplies one page's worth of addresses to the image memory write control section 42, data writing of one page's worth of virtual pages to the image memory 30 is completed. Then, data for the next virtual page is written.

Data Write Operation> Here, the data write operation will be explained in more detail.

First, when an attempt is made to write data for the first word of one block, the address generator 43 outputs the word address. The upper bits of this word address constitute a virtual block address, and the lower bits constitute an intra-block address.

When the one word is determined to be blank data by the data determining section 41, writing to the image memory 30 is not performed regardless of whether this block is a blank block or a valid block. Then, when the next one word of data is accessed, the intra-block address is incremented while the virtual block address remains unchanged.

If this data for one word is again blank data, writing to the image memory 30 is not performed as before, and after some words have been accessed, valid data is accessed this time. do. The data determination section 41 outputs a determination result that the data is valid data to the image memory write control section 42 .

Here, for the first time, the mapping flag of the corresponding virtual block address is rewritten from 0 to 1 in the address conversion unit 44. Then, a block address in the image memory 30 to which the data is to be written is determined. This is,
It is written into the address conversion memory 44a. As explained earlier, the block address of the image memory 30 obtained by this address conversion is stored in the image memory write control unit 4.
It is saved in a register etc. within 2.

After the block address of the image memory is determined in this way, the lower bits corresponding to the intra-block address in the word address are added to the block address of the image memory 30, and one word worth of information is transferred to the image memory 30. Used to write valid data.

When the next data is read from the block of the virtual page 61, if it is valid data, the virtual block address is compared with the previous virtual block address.0 If the two match, the image memory write control unit 42 The block address of the image memory stored in the image memory is used as it is, the address within the block is added thereto, and valid data is written into the image memory.

After that, for example, if blank data is input to the data determination unit 41 again, no writing is performed. Note that when writing is not performed, the data at the corresponding address in the image memory 3o is in the initial state, that is, data having the same content as blank data.

In this way, the block address of the image memory stored in the image memory write control section 42 is used until the last word of data of one block is read out. That is, for one block, the address translation memory 44a only needs to be referenced once.

Note that the order of the addresses generated by the address generator 43 is not defined, and there is no problem whether they are sequential or random. Furthermore, there is no problem whether the address to be generated can be all or part of one page of the virtual page.

<Data read operation> In parallel with these writes, printing of the already written page can be executed. In this case, first,
The address generation unit 43 shown in the figure generates word addresses in raster unidirectional order of the virtual page 61.The zero image memory write control unit 42 generates the address of the address conversion unit 44 based on the virtual block address, which is the upper bit of this word address. Conversion memory 44 a l! ! ,refer.

Here, if the mapping flag T corresponding to the virtual block address is 1, the corresponding image memory 3
Referring to the block address RM of 0, the image memory 30
All data included in the effective block is read out from the block, and print data is output to the printing section 50 via the connection switching circuit 45.

Also, referring to the address conversion memory 44a, if the mapping flag T is zero, the image memory write control unit 42 generates blank data for that one block by itself, and sends this to the connection switching circuit 45. It is output to the printing unit 50 via the printer.

Note that the address determination unit 8o compares and determines the virtual block address generated by the address generation unit 43 with the virtual block address accessed immediately before, and similarly to writing, the image memory write control unit 42 determines whether the virtual block address is unnecessary or not. This prevents repeated address translations.

If we perform this operation sequentially in units of l blocks, we get
As shown in FIG. 9, the image on the virtual page 61 can be reproduced as a printout. When the reading is completed, the mapping flag T and page identification flag of that virtual page are all cleared to zero, making it possible to write the next virtual page.

Variant example The present invention is not limited to the above embodiments.

As described above, the address conversion unit 44 associates the virtual block address in the virtual page 6 of the valid block with the block address of the image memory 30 in which the valid block is written, and also A mapping flag for identifying blocks and blank blocks may be provided, and a page identification flag may be provided for identifying a virtual page to which a valid block written in the image memory belongs.

Therefore, as shown in FIG. 1, it is not necessarily necessary to separately provide the address conversion memory 44a and the free block instruction memory 44b.

FIG. 1 shows a modification of the address translation section.

This address translation unit sets page identification flags PI, P2Ps, Pa in correspondence with the virtual block address.
Mapping flag T and image memory block address R
M and are stored in a table.

Here, the address conversion section is constructed on the assumption that, for example, four virtual pages (for normal images, the limit is about four pages at most) are stored in the image memory. That is, the page identification flag is 4 bits P1 to P4, the mapping flag T is 1 bit, and the remaining 11 bits.
A bit block address RM is prepared.

If such a table is stored in the memory of the address translation section 44, the processing explained in FIG. 1 will be executed.

By combining the table data into one in this way, the control signals can be simplified and the memory capacity can also be reduced, making it possible to highly integrate this circuit (LSI). Furthermore, if the mapping flag T is encoded, the mapping flags for four pages can be displayed in 2 bits.

Furthermore, if the content of the virtual page is simpler, more virtual pages can be written to one page of the image memory 30.

FIG. 12 shows a modification of the address translation unit when writing a large number of virtual pages in this way.

The data width of the address conversion section is 16, which is the same as that in Figure 1.
Here, take the necessary number of bits for the page identification flags P and ~Px, then take 1 bit from the mapping flag T, divide the block address RM into two, and include the next 16 bits of data. 1 block address is displayed. In this case, it goes without saying that virtual block addresses are set every other block.

By such a method, the configuration of the address conversion section 44 itself can be simplified, and the operation of the image memory write control section 42 can be simplified.

In addition, the present invention provides that the configuration of the printing section is not limited to electrophotography.
The present invention may be applied to any method such as a thermal printer method or a wire dot method. Further, the print control section may be replaced with various circuits having similar functions.

(Effects of the Invention) According to the printing apparatus of the present invention as described above, printing data for two or more pages can be stored using a relatively small capacity image memory, for example, for one page, and address can be efficiently addressed. Once the conversion is completed, printing can be performed at high speed without any waiting time. Furthermore, the cost of the printing device can be reduced by reducing the memory capacity.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the printing apparatus of the present invention;
FIG. 2 is a block diagram of a conventional printing device, FIG. 3 is a conceptual diagram illustrating control of reading print output from a conventional image memory, and FIG. 4 is a specific example of the operation of reading print output from a conventional image memory. An explanatory diagram explaining an example, FIG. 5 is an explanatory diagram of the operation of the print engine, FIG. 6 is a time chart explaining the writing/reading timing of the conventional image memory, and FIG.
8 is a time chart illustrating a write operation of a conventional image memory, FIG. 8 is a time chart illustrating a desirable write operation of an image memory, and FIG. FIG. 10 is a detailed operational explanatory diagram of the address translation section of the device of the present invention, and FIGS. 11 and 12.
The figure is an explanatory diagram showing a modification of the address translation section of the present invention. 30... Image memory, 4o... Print control unit, 41.
...Data determination unit, 42...Image memory write control unit, 43...Address generation unit, 44...Address conversion unit, 44a...Memory for address conversion, 44b...Memory for empty block instruction , 45... Connection switching circuit, 50... Printing section, 60... Printing data, 8o... Address determination section, 80a... Register, 8ob... Comparator, 61... Virtual Page, 62・
...Block, T...Mapping flag, RM...Image memory block address, Pt, Pa...
-Px...Page identification flag. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Scope of Claims] An image memory that stores print data, a print control unit that writes print data into the image memory, and a print unit that performs printing while reading print data from the image memory. , the print control unit divides a virtual page consisting of one page of images virtually set in correspondence with print output into a plurality of blocks;
a data determination unit that determines whether data included in each block of the virtual page is blank data or valid data; and when the address of each block in the virtual page is called a virtual block address, a virtual block of accessed data; an address determining unit that determines whether the address is the same as or different from a virtual block address of data accessed immediately before; and an address determining unit that determines whether the address is the same as or different from a virtual block address of data accessed immediately before; and based on the determination result of the data determining unit, only the valid data is selected and stored in the image memory. an image memory write control unit that writes data; associates the virtual block address to which the valid data has been written with the block address of the image memory to which the valid data has been written; and ,
an address storing a mapping flag that identifies the valid block containing the valid data and the blank block consisting only of the blank data; and a page identification flag that identifies the virtual page to which the valid block written in the image memory belongs. a converter is provided, and when accessing the data, the image memory write control unit converts the address based on the judgment result of the address judgment unit if the virtual block address of the data accessed immediately before is included. 1. A printing device, characterized in that the printing device performs address translation by referring to the previous data, and if the virtual block address of the data accessed immediately before is the same, the address translation result at the time of accessing the data immediately before is used.