JPH02270190A - Integrated circuit containing grich protecting circuit - Google Patents

Abstract

PURPOSE: To prevent output of glitch by providing a non-symmetrical delay filter between a control signal circuit and a circuit controlled by the signal. CONSTITUTION: A chip-enable-input 2 is connected to an input of a NAND gate 4, and an output of the NAND gate is connected to an output buffer control 6. A non-symmetrical delay circuit in which delay is slow at the time of ENABLE and fast at the time of DISABLE, that is, an inverter chain 8 is provided between the chip-enable-input 2 and the output control 6. Thereby, length of a delay time can be adjusted in accordance with width of glitch to be suppressed by increasing/decreasing the number of inverters of the inverter chain 8, the non-symmetrical delay filter can be used for protecting the device so that glitch does not causes an undesirable result.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to integrated circuits, particularly semiconductor memories. This invention was awarded under Contract No. DNA by the Defense Nuclear Administration.
Sponsored by the United States Government under No. 0O1-86-0090.

BACKGROUND OF THE INVENTION Noise or "glitches" in integrated circuit system signals can cause undesirable results. This is a particularly important problem with memory in microprocessor systems. In chips where a chip enable (CE) input signal is used to keep the output at a high impedance, a glitch in the chip enable causes the output to transition to a low impedance state for the duration of the glitch. This creates a problem called path contention. In other words, 2g or more of memory drives the bus at the same time. This phenomenon is especially caused by static random
Problems tend to occur when access memory (SRAM) is under transient conditions. -Other glitches that occur in random logic circuits can be attributed to collisions of ionized particles.

OBJECT AND SUMMARY OF THE INVENTION It is an object of the present invention to provide new and improved applications for glitch protection circuits.

Another object of the invention is to provide a new and improved use of asymmetric delay circuits for glitch protection.

The above object is achieved by providing an asymmetric delay filter between the control signal and the circuit controlled by the signal. The delay of the filter can be matched to the delay of other inputs to the circuit so that the delay has minimal impact on overall performance.

Embodiment FIG. 1 shows a schematic diagram of a preferred embodiment of the present invention providing glitch protection. In FIG. 1, the chip enable power 2 is connected to the input of the Nante gate 4, and the Nante gate 4
The output of is connected to the output sofa control 6. The present invention provides protection against the above-mentioned overhearing by eliminating enable pulses that are shorter than a predetermined time width. This predetermined time width is, for example, equal to the processing time of another logic circuit connected between the chip enable input 2 and the buffer control 6. Therefore, it is possible to process inputs to the buffer control 6 simultaneously. This other logic circuit is, for example, a general logic circuit for memory. - A standard logic circuit can handle address inputs and word line inputs, for example as shown. Glitches can be eliminated by providing an asymmetrical delay circuit between the chip enable input 2 and the output control 6 that is slow when enabled and fast when disabled. (Asymmetrical delay means that there is a difference in delay between a signal that transitions from high to a- and a signal that transitions from low to high.) In Figure 1, an asymmetrical delay circuit is realized by an inverter chain 8. ing.

Input of inverter chain 8 is chip enable human power 2
The output is connected to the input of the Nantes gate 4. By increasing or decreasing the number of inverters in the inverter chain 8, the length of the delay time can be adjusted depending on the width of the glitch to be suppressed. The length of the delay time can also be reduced by 51 nodes by connecting a capacitor in parallel with one or more inverters.

As long as the delay time is less than the time required to produce the proper output from the chip enable, the delay does not impair chip performance.

In a memory such as an SRAM, the asymmetric delay circuit described above can be applied to a 1-inclusive signal. In this case, the delay time is matched to the set-up time during address decoding. FIG. 2 is a block diagram of such a case, in which an asymmetrical delay filter is connected between the self-write enable circuit and the write control circuit. The write control circuit has address tI.
The IItl input is also connected. FIG. 3 shows the operation of the circuit of FIG. 2. FIG. 3 is a timing diagram of high/low or low/high transition logic, shown for the data bus, address decode, write enable signal, and southbound control signal. The time axis is shown in microseconds. The trend control is 0 until the address decode has completely reached F, indicating that the address decode has ended.
- does not turn on.

Depending on the trade-off between glitch protection versus memory access speed requirements, asymmetric delay protection may also be applied to other signals connecting, for example, from chip enable to circuitry other than output buffer control.

Asymmetric delay filters can be used to protect glitches in certain portions of an integrated circuit chip from producing undesired results. For example, in a memory controller chip, it may be most important not to inadvertently issue an "output enable" signal.

By inserting an asymmetric delay filter between the logic circuit and the output buffer 7, it would be possible to prevent glitches occurring within the logic circuit from being output. A schematic diagram of such a case is shown in FIG. This figure shows a memory controller with logic circuitry connected to an output buffer via an asymmetrical delay filter.

Output buffers send data onto the bus. The filter is resistant to unexpected noise. For example, if the unexpected noise source is a transient radiated pulse, a current compensation device can be used within the filter circuit and a separate power bus can be provided to the filter circuit to avoid rail span collapse. It is more efficient to introduce an asymmetric delay filter to protect that part from transition dose effects than to protect all other circuits in the memory controller system from transition dose effects.

Figures 5a and 5b illustrate another embodiment of the invention that provides glitch protection. In FIG. 5a, an inverter chain 8 is connected to the input of the Nandt gate 4 and to the input IN.

The input IN is also connected to the input of the Nant gate 4.

The circuit of FIG. 5a is active when a high-transitioning glitch comes into input IN. For example, when input IN is initially low level and node A is also low level, input IN
Even if A transitions to high, the output of NAND 4 does not respond until node A goes high. After a predetermined time 1Ilp set by the inverter chain 8, the node changes to high. However, the inverter chain 8 can be replaced by another delay circuit, including an RCl network or the like. If the input lN5u- state is returned before the given delay node A goes high, the output OUT will not react at all to the transition that initially occurred on IN (OLIT remains high). . Conversely, if the input IN is initially high (fil) and the output OUT is low (1) and then changes to a low state, the output OUT changes to a high state regardless of the delay. Figure 5b. is the same as FIG. 5a except that a NOR gate 5 is used in place of the Nandt gate 4 of FIG. 5a.The circuit of FIG. The operation of the circuit of Figure 5b is similar to the circuit of Figure 5a. As previously mentioned, the inverter chain can be replaced with other delay paths such as an RC network. The number of inverters shown in Figures 5a and 5b can be increased or decreased to obtain the delay time.

FIG. 5C shows another embodiment of the invention. In this example, there is a glitch removal effect when transitioning in either direction. This circuit is suitable for use with clocked signals. Figure 5C is a combination of the circuits in Figures 5a and 5b, in which the input input IN is common, and the outputs of the Nant gate 4 and the Nor gate 5 are an n-channel transistor and an n-channel transistor connected in parallel, respectively. connected to the first drain/source of the pair consisting of: N-channel transistor 20 and n-channel transistor 22 are the first
forming a transistor set of n-channel transistor 2
4 and n-channel transistor 26 form a second transistor set.

Inverter 16 is connected to input IN and to the input of inverter 18 and drives the gates of transistors 20 and 24. Inverter 18, on the other hand, drives the gates of transistors 22 and 26.

The second drain/source of transistors 22 and 26 forms the output 0LIT. This bidirectional glitch protection circuit can be applied to signals where the delay can be longer than the glitch. For example, if the output is allowed to delay in three states (output includes high, low, and transient states) after the chip is released, use this circuit between the chip enable and the output enable in the SRAM. be able to.

FIG. 6 shows yet another embodiment of the invention. FIG. 6 is a bidirectional circuit including a transition detection circuit and a latch. The first and second transistor sets are connected as in FIG. 5C, but with inverter 18 removed and inverter 40
and 42 are connected in series to the second drains of two sets of transistors/
The difference is that it is connected to the source. Address transition detection circuit 32 and asymmetric delay circuit 12 are connected to input IN. The latches are elements 16, 20, 22.24°26.
Consists of 40.42. However, other types of latches can also be used. Address detection circuits generate positive going pulses when they detect transitions, but latch circuits can be designed to also use negative pulses. The asymmetric delay circuit 12 accommodates the delay time from input INIfili to being latched into the latch circuit (thereby being somewhat longer). The width of the pulses generated by transition detection circuit 32 must be adjusted to be comparable to the width of the glitch to be removed.

If a node in a logic circuit is hit by a high-energy particle, the voltage will fluctuate over time but will recover. This creates glitches in the signal. If the glitch latches, it becomes a permanent error. This situation can be avoided by providing an asymmetrical delay circuit as described above at the input of the latch.

If an asymmetrical delay filter is consistently placed on the clock signal, the cycle time does not change because all clocks are delayed uniformly. For example, as shown in FIG. 7, if the clock board system has the same clock as 1. II controlled multiple chips (microprocessor, SRAM,
an asymmetrical delay filter can be provided at the clock input of each chip. This idea can also be applied to clocks inside the chip. If the clock is glitch-proof, all inputs to the latch should be glitch-proof! An IF circuit can be provided. That way, all gate inputs would be delayed by the same amount of time, so there would be no speed reduction for protection.

The only burden is that the area becomes larger (additional circuit space is required). Alternatively, the glitch protection circuit may be provided within the clock generation circuit, for example, between the zero clock generation logic and the clock driver. Because the capacitance is large, even if ionization occurs, glitches are less likely to occur on large drivers. The same applies to the clock driver; for signals with large capacitance, the glitch protection 11 circuit may be provided immediately before the large driver instead of being provided at the latch input.

FIG. 8 shows yet another embodiment of the invention. Word IIa
A control signal W is input to the asymmetric delay filter.

A data input and a column address input are input to logic circuit 50. An asymmetrical delay filter and logic circuit 50 are connected to column drive logic, which controls the memory array circuitry. Because of the asymmetric delay filter, the column drive circuit can process the output of the logic circuit 50 and the word line control signal W simultaneously.

Although the present invention has been described in detail with respect to preferred embodiments and alternative examples thereof, this description is merely an example.
It does not have a limited meaning.

After reading this description, those skilled in the art will be able to easily make various modifications and additions. Such modifications and additions are considered to be within the scope of this invention. Therefore, the scope of the invention should be determined in accordance with the claims.

Regarding the above description, the following sections are further disclosed.

(1) An integrated circuit comprising: a chip enable input; an output buffer enable circuit; and an asymmetric delay filter connected between the chip enable input and the output buffer enable circuit.

(2) A memory chip including the integrated circuit described in item (1).

(3) In the case described in paragraph (2), the memory is a static random access memory;
memory chip.

(4) The device according to paragraph (2), wherein the memory is a dynamic random access memory.
memory chip.

(5) A memory chip in the device according to item (2), wherein the memory is a read-only memory.

(6) In the device according to paragraph (1), the delay of the asymmetric delay filter serves to prevent the output buffer enable from working effectively when a chip enable pulse shorter than a predetermined pulse width is generated. integrated circuits.

(7) An asymmetrical delay filter in the device according to paragraph (1), comprising an inverter including an inverter input and an inverter output, and a Nant gate including first and second Nant gate inputs, and the inverter output is connected to the first Nandt gate input, and the inverter input is connected to the second Nandt gate input.

(8) Write enable input and write! ill
m1 circuit, the write enable input and the -write t
an asymmetric delay filter connected between an ilII11 circuit.

(9) A memory chip including the integrated circuit described in item (8).

(10) The device according to item (9), wherein the memory is a static random access memory.

(11) In the device according to item (9), the memory chip is a read-only memory.

(12) In the device according to paragraph (8), the delay of the asymmetric delay filter is such that the write i
ll ￥a An integrated circuit that serves to prevent the circuit from working effectively.

(13) An asymmetrical d-paper filter in the device according to item (8), comprising an inverter including an inverter input and an inverter output, and a Nant gate including first and second Nant gate inputs; an output is connected to the first Nant gate input, and the inverter input is connected to the second Nant gate input;
Asymmetric delay filter.

(14) An integrated circuit including a clock generation circuit, a clock driver, and an asymmetric delay filter connected between the clock generation circuit and the clock driver.

(15) A memory chip comprising the integrated circuit according to item (10).

(16) The device according to paragraph (15), wherein the memory is a static random access memory.
memory chip.

(11) In the device according to paragraph (15), the memory is a dynamic random access memory.
memory chip.

(18) In the device according to item (15), the memory chip is a read-only memory.

(19) In the device according to item (14), the delay of the asymmetric delay filter is such that the clock driver does not work effectively when a clock pulse shorter than a predetermined pulse width is generated from the clock generation circuit. Integrated circuits that play a role in preventing

(20) 1(14) Item 11 is a %lL-o-GJ6 asymmetric U-broadcast filter, comprising an inverter including an inverter input and an inverter output, and a Nant gate including first and second Nant gate inputs. an asymmetric delay filter, wherein the inverter output is connected to the first Nandt gate input, and the inverter input is connected to the second Nandt gate input.

(21) The asymmetric delay filter is configured to operate in G mode upon receiving the control signal, and is connected to a circuit controlled by the control signal, and the delay of the filter is the delay of the other input of the circuit. Integrated circuits that match.

(22) discloses an integrated circuit using an asymmetric delay circuit to suppress "r glitches". This integrated circuit is, for example, a static random access memory, S
RAM. Specifically, an asymmetric delay circuit is used to ensure that glitches on the "chip select" signal do not appear as glitches on the output enable signal. At this time, the grip is suppressed without impairing the performance of the SRAM. A bidirectional glitch protection circuit is also disclosed. This circuit is particularly effective in glitch protection against SEU.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a preferred embodiment of the present invention. FIG. 2 is a block diagram showing a case where an asymmetrical delay filter is connected between a write enable circuit and a 1-write control circuit. FIG. 3 is a timing diagram showing the transition of the data bus, address decode, write enable signal, and write control signal to logic high/low or low/high in time axis [1 second]. FIG. 4 shows a memory controller in which logic circuits are connected to an output buffer via an asymmetric delay filter. Figures 5a and 5
Figure b shows another embodiment of the invention that provides glitch protection. FIG. 5C shows another embodiment that protects against glitches in either direction. FIG. 6 is still another embodiment of the present invention, and is a diagram showing a bidirectional circuit comprising a transient protection circuit and a latch. FIG. 7 is a diagram showing still another embodiment of the present invention.
It is used when a plurality of all chips are housed in one clock board system. FIG. 8 is a diagram illustrating still another embodiment of the present invention, in which the word Ill m signal is inputted so that the output read m control signal of the logic circuit can be processed by the column drive circuit at the same time. It is input to an asymmetric delay filter.

Claims (1)

[Claims] (1) An integrated circuit comprising: a chip enable input; an output buffer enable circuit; and an asymmetric delay filter connected between the chip enable input and the output buffer enable circuit.