JPH02270349A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02270349A
JPH02270349A JP9141089A JP9141089A JPH02270349A JP H02270349 A JPH02270349 A JP H02270349A JP 9141089 A JP9141089 A JP 9141089A JP 9141089 A JP9141089 A JP 9141089A JP H02270349 A JPH02270349 A JP H02270349A
Authority
JP
Japan
Prior art keywords
wiring material
film
wiring
insulating film
grounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9141089A
Other languages
Japanese (ja)
Inventor
Tadashi Yasue
匡 安江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP9141089A priority Critical patent/JPH02270349A/en
Publication of JPH02270349A publication Critical patent/JPH02270349A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent problems, such as the deterioration of the characteristics of a circuit due to the electrostatic coupling between wiring materials and between a wiring material and an element, an erroneous operation and the like, from generating by a method wherein a first conductor film and a second conductor film are connected to each other through an opening part provided in first and second insulating films on the side on one side of the wiring material and at the same time, are grounded. CONSTITUTION:A semiconductor device is constituted of a first conductor film 6 formed on a substrate, a wiring material 3 formed through the film 6 and a first insulating film 2 and a second conductor film 8 formed through the material 3 and a second insulating film 4 and the above films 6 and 8 are connected to each other through opening parts 7 provided in the films 2 and 4 on the side on at least one side of the above material 3 and at the same time, are grounded. Thereby, problems, such as the deterioration of the characteristics of a circuit due to the electrostatic coupling between the wiring material surrounded with the grounded conductor films and other wiring material and between the wiring material and an element, an erroneous operation and the like, are not generated and as the restrains of the wiring material are eliminated, an increase in the integration of a semiconductor device becomes possible.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置に係り、特に、多層配線が可能で
ある半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device capable of multilayer wiring.

〔従来の技術1 近年、半導体装置の高集積化にあたり、素子間の配線が
高密度化、多層化しているが、従来は。
[Prior Art 1] In recent years, as semiconductor devices have become more highly integrated, the wiring between elements has become denser and multilayered.

例えば、第2図に示すように、基板上に形成された配線
材1の上に、絶縁1t@2を介して配線材3が形成され
、さらに絶縁膜4を介して配線材5が形成される構造を
とっていた。
For example, as shown in FIG. 2, a wiring material 3 is formed on a wiring material 1 formed on a substrate through an insulation 1t@2, and a wiring material 5 is further formed through an insulating film 4. It had a structure that

(発明が解決しようとする課題1 しかしながら、第2図に示されるような従来の構造では
、各配線材間及び素子との間の静電結合により、回路の
特性の劣化や誤動作等の問題が発生する。そのため、各
配線材の配置に大きな制約ができ、半導体装置の高集f
a化の妨たげとなっていた。
(Problem to be Solved by the Invention 1) However, in the conventional structure shown in Fig. 2, problems such as deterioration of circuit characteristics and malfunction occur due to electrostatic coupling between each wiring material and between elements. As a result, there are significant restrictions on the placement of each wiring material, and the high concentration of semiconductor devices
This was an obstacle to becoming a.

そこで本発明は、このような課題を解決することを目的
とする。
Therefore, an object of the present invention is to solve such problems.

[課題を解決するための手段] 基板上に形成された第1の導電体膜と、前記第1の導電
体膜と第1の絶縁膜を介して形成された配線材と、前記
配線材と第2の絶縁膜を介して設置された第2の導電体
膜とから構成され、前記第1の導電体膜及び第2の導電
体膜とが、前記配線材の少なくとも一方の側において前
記第1の絶縁膜及び第2の絶縁膜に設けられた開口部を
通して接続されるとともに接地されることを特徴とする
[Means for solving the problem] A first conductive film formed on a substrate, a wiring material formed via the first conductive film and a first insulating film, and the wiring material. a second conductor film installed through a second insulating film, and the first conductor film and the second conductor film are arranged on at least one side of the wiring material. It is characterized in that it is connected and grounded through openings provided in the first insulating film and the second insulating film.

〔実 施 例1 以下、本発明の一実施例を図面に基づいて説明する。[Implementation example 1] Hereinafter, one embodiment of the present invention will be described based on the drawings.

まず、第1図に示す断面図では、基板上に形成された導
電体膜6および配線材1の上に、絶!1llI2を介し
て配線材3を形成し、配線材と絶縁膜4を介して導電体
膜8を形成する。ここで、導電体膜6と8は、絶縁11
12.4に設けられた開口部7を通して接続されている
とともに、電源ラインの基準電位等に接続されている。
First, in the cross-sectional view shown in FIG. A wiring material 3 is formed through the 1llI2, and a conductive film 8 is formed through the wiring material and the insulating film 4. Here, the conductor films 6 and 8 are insulating 11
12.4 through the opening 7 provided therein, and is also connected to the reference potential of the power supply line, etc.

その導電体膜8上に絶縁1119を介して配線材5を形
成する構造をとっている。
A structure is adopted in which the wiring material 5 is formed on the conductor film 8 with an insulator 1119 interposed therebetween.

なお、配線材が3層以上用いられるならば、そのうち・
の2つの層の一部分を、接地された導電体膜として兼用
することも可能である。
In addition, if three or more layers of wiring material are used,
It is also possible to use a portion of the two layers as a grounded conductor film.

[発明の効果] 以上説明したように、本発明によると、接地された導電
体膜で囲まれた配線材と、他の配線材及び素子との間の
静電結合が生じないため、その静電結合による回路の特
性の劣化や誤動作等の問題が発生しないとともに、配線
材の配置の制約が解消されるため、半導体装置の高集積
化が可能となる。
[Effects of the Invention] As explained above, according to the present invention, since no electrostatic coupling occurs between the wiring material surrounded by the grounded conductive film and other wiring materials and elements, the static Problems such as deterioration of circuit characteristics and malfunction due to electrical coupling do not occur, and restrictions on the arrangement of wiring materials are eliminated, making it possible to increase the integration of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例である半導体装置の断面図、
第2図は従来の半導体装置の断面図である。 l・・・配線材 2・・・絶縁膜 3・・・配線材 4・・・絶縁膜 5・・・配線材 6・・・接地された導を体膜 7・・・絶縁膜に設けられた開口部 8・・・接地された導電体膜 9・・・絶縁膜 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴 木 喜三部(使1名);l ノ 
リリ Iλa
FIG. 1 is a cross-sectional view of a semiconductor device which is an embodiment of the present invention.
FIG. 2 is a sectional view of a conventional semiconductor device. l...Wiring material 2...Insulating film 3...Wiring material 4...Insulating film 5...Wiring material 6...Grounded conductor is provided on body film 7...Insulating film Opening 8...Grounded conductive film 9...Insulating film and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (1 representative);
Lily Iλa

Claims (1)

【特許請求の範囲】[Claims] 基板上に形成された第1の導電体膜と、前記第1の導電
体膜と第1の絶縁膜を介して形成された配線材と、前記
配線材と第2の絶縁膜を介して形成された第2の導電体
膜とから構成され、前記第1の導電体膜と第2の導電体
膜とが、前記配線材の少なくとも一方の側において、前
記第1の絶縁膜及び第2の絶縁膜に設けられた開口部を
通して接続されるとともに接地されることを特徴とする
半導体装置。
A first conductive film formed on a substrate, a wiring material formed through the first conductive film and a first insulating film, and a wiring material formed through the wiring material and a second insulating film. the first insulating film and the second electrically conductive film, and the first electrically conductive film and the second electrically conductive film are connected to each other on at least one side of the wiring material. A semiconductor device characterized in that it is connected and grounded through an opening provided in an insulating film.
JP9141089A 1989-04-11 1989-04-11 Semiconductor device Pending JPH02270349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9141089A JPH02270349A (en) 1989-04-11 1989-04-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9141089A JPH02270349A (en) 1989-04-11 1989-04-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02270349A true JPH02270349A (en) 1990-11-05

Family

ID=14025608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9141089A Pending JPH02270349A (en) 1989-04-11 1989-04-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02270349A (en)

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