JPH0362555A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the influence of unnecessary signals produced by the intersection between polycrystalline silicon and metallic wiring to circuit operations by applying the highest or lowest electric potential across prescribed metallic wiring as a bias voltage. CONSTITUTION:Metallic wiring 2a insulated from polycrystalline silicon 1 and metallic wiring 2b formed on a semiconductor substrate 4 by means of oxide films 3a and 3b is provided between the silicon 1 and wiring 2b. The wiring 2a biases the highest or lowest electric potential of a power source on an integrated circuit. Then a capacitor which uses the film 3a as a dielectric body and the silicon 1 and wiring 2a as both poles and another capacitor which uses the film 3b as a dielectric body and the wiring 2b and 2a as both poles are respectively formed. Therefore, the mutual interference between the silicon and metallic wiring can be shielded by means of the metallic wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a resistor formed of polycrystalline silicon, a wiring, and a wiring that intersects with the gate of a MOS transistor.

[Conventional technology]

FIG. 3 is a sectional view of a semiconductor chip showing an example of the structure of a conventional semiconductor device, and FIG. 4 is an equivalent circuit diagram of FIG. 3. Conventionally, in this type of semiconductor device, as shown in FIG. 3, when a metal wiring 2 is formed crossing over polycrystalline silicon 1 formed on a semiconductor substrate 4, there is no space between the two. It is necessary to form an oxide film 3 to insulate the. By forming this oxide 11i3, as shown in FIG. 4, a capacitor C is formed which has the oxide film as a dielectric and polycrystalline silicon and metal wiring as both poles.

[Problem to be solved by the invention]

In the structure of the conventional semiconductor device described above, since a capacitor is formed using an oxide film as a dielectric and polycrystalline silicon and metal wiring as electrodes, interference occurs between the polycrystalline silicon and the metal wiring. That is, unnecessary signals are generated on the circuit, which causes malfunction of the circuit.

An object of the present invention is to provide a semiconductor device that eliminates such drawbacks.

[Means to solve the problem]

The semiconductor device of the present invention has a metal wiring formed with an insulating film interposed between the wiring made of polycrystalline silicon and the metal wiring formed overlappingly on a semiconductor substrate. Alternatively, it is characterized by applying the lowest potential.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the semiconductor device of the present invention, and FIG. 2 is an equivalent circuit diagram of FIG. 1.

This semiconductor device has a semiconductor substrate 4 as shown in FIG.
The metal wiring 2a is provided between the polycrystalline silicon 1 formed above and the metal wiring 2b, which is insulated from both by oxide films 3a and 3b. Further, this metal wiring 2a is biased at the highest or lowest potential of the power supply on the integrated circuit of the semiconductor device. With such a structure, a capacitor with the oxide film 3a as a dielectric and the polycrystalline silicon 1 and the metal wiring 2a as both poles, and a capacitor with the oxide film 3b as the dielectric and the metal wiring 2b and the metal wiring 2a are formed.
A capacitor is formed with both poles.

The state in which this capacitor is formed is shown in an equivalent circuit as follows:
It will look like Figure 2. That is, as shown in the figure, unnecessary signals generated by capacitors C1 and C2 can be passed through electrode C by connecting electrode C to the highest or lowest potential of a low impedance power source on the IL product circuit. , electric iA, B, and Bl.

〔Effect of the invention〕

As explained above, in the present invention, when a resistor or wiring formed of polycrystalline silicon and a gate of a MOS transistor intersect with a metal wiring, an oxide film is provided between the polycrystalline silicon and the metal wiring to protect both. By forming the metal wiring that is insulated and biased by the highest or lowest potential of the power supply on the integrated circuit, the metal wiring shields the polycrystalline silicon and the metal wiring from mutual interference, and the polycrystalline silicon and the metal wiring This has the effect that a semiconductor device can be obtained in which unnecessary signals caused by the intersection of the two do not affect the circuit operation.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the structure of a semiconductor device of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1,
FIG. 3 is a sectional view of a semiconductor chip showing an example of the structure of a conventional semiconductor device, and FIG. 4 is an equivalent circuit diagram of FIG. 3. 1... Polycrystalline silicon, 2.2a, 2b... Metal wiring, 3.3a, 3b... Oxide film, 4... Semiconductor substrate.

Claims (1)

[Claims] A metal wiring is formed with an insulating film interposed between the polycrystalline silicon wiring formed on a semiconductor substrate and the metal wiring, and the highest or lowest potential in the device is applied to this metal wiring. Characteristic semiconductor devices.