JPH02274015A - Double sample-hold circuit - Google Patents

Abstract

PURPOSE:To reduce the settling time by alternately bringing a first sample-hold circuit and a first switch, and a second sample holding circuit and a second switch to switching control. CONSTITUTION:A first switch 3 is connected to a first sample-hold circuit 1 for extracting and holding an analog input signal to an analog/digital(A/D) converter 7, and a second switch 4 is connected to a second sample-hold circuit 2 for executing an alternate operation with a first sample-hold circuit 1 and and extracting and holding an analog input signal to the A/D converter 7. The switches 3, 4 alternately connect a first sample-hold circuit 1 and a second sample-hold circuit 2 to the A/D converter 7. Also, a sample-hold control circuit 6 controls so as to alternately switch and connect a first sample-hold circuit 1 and a first switch, and a second sample-hold circuit 2 and a second switch 4. In such a way, the settling time is reduced.

Description

[Detailed Description of the Invention] (Summary) Regarding a sample hold circuit connected to the front stage of an analog/digital converter, the purpose of this invention is to reduce the settling time of the sample hold circuit. a first sample-and-hold circuit that extracts and holds a sample; and a second sample-and-hold circuit that operates alternately with the first sample-and-hold circuit; a first switch and a second switch that alternately connect the analog/digital converter to the analog/digital converter, the first sample and hold circuit and the first switch, and the second sample and hold circuit and the second switch. and are configured to be alternately switched and controlled by a sample and hold control circuit.

[Industrial application field]

The present invention relates to a sample and hold circuit connected upstream of an analog/digital converter.

An analog/digital converter (A/D converter) that converts an analog signal into a digital signal often has a sample and hold circuit additionally connected to the front stage in order to extract and hold the analog signal.

When performing analog/digital conversion, the conversion time is A
/D converter, but the settling time of the sample and hold circuit installed before the converter cannot be ignored in high-speed operation.
It has become necessary to speed up analog/digital conversion in (extraction).

[Conventional technology]

FIG. 5 shows a circuit configuration diagram of a sample and hold circuit of a conventional A/D converter. In the figure, 11 is a sample hold circuit, 12 is an A/D converter, 13 is a sample control switch, 14 is a capacitor, and I5 is a buffer amplifier.

The sample and hold circuit 11 includes a sample control switch 13 that is turned on and off by sample pulses, a capacitor 14 that stores an analog input voltage, and a buffer amplifier 15 that compares it with an output feedback voltage.

The A/D converter 12 is a circuit that converts the analog voltage extracted and held from the sample and hold circuit 11 into a digital value and sends it out.

The analog input signal voltage is stored in the capacitor 14 when the sample control switch 13 is turned on, and the stored input voltage is stored in the buffer when the sample control switch 13 is turned off.
The analog voltage extracted and held by the amplifier 15 and extracted and held by the A/D converter 12 is input, and a digital value corresponding to the analog voltage is output. Next, when the sample control switch 13 is turned on again, the analog voltage at the next point in time is input and stored in the capacitor 14, and when the sample control switch 13 is turned off, the next stored input voltage is extracted and held in the buffer amplifier 15. is,
The extracted and held analog input terminal is input to the A/D converter 2, and a digital value corresponding to the analog voltage is output. In this way, the analog input voltage is extracted and held each time by turning on and off the sample control switch 13, and a digital value corresponding to the input voltage is output. Therefore, a digital value is output in response to a change in the analog input terminal, and an analog signal can be converted into a digital signal.

FIG. 6 shows an analog signal extraction and holding characteristic diagram of the conventional sample and hold circuit. In the figure, H indicates a hold mode state in which the sample control switch is turned off, and S indicates an extraction state, that is, a sample mode state, when the sample control switch is turned on.

The time for sample mode state S to transition from hold mode state H to the next hold mode state H is set (
convergence) time, and if this settling time is long, A
This will interfere with the high-speed operation of the /D converter.

[Problems to be Solved by the Invention] In the conventional sample-and-hold circuit, the time from one hold mode to the next hold mode, that is, the time in the sample mode, is required for settling. This may cause problems.

The present invention provides two sets of sample and hold circuits and alternately switches them so that one is in hold mode and the other is in sample mode, thereby reducing the settling time from one hold mode to the next. The purpose is to

(Means for Solving the Problems) The principle configuration diagram of the present invention is shown in Fig. 1. In the figure, 1 is a first sample and hold circuit, 2 is a second sample and hold circuit, 3 is a first switch, 4 is the second switch,
5 is an inverter, 6 is a sample and hold control circuit, and 7 is an A/D converter.

The sample and hold circuit 1 is a first sample and hold circuit that extracts and holds an analog input signal to the A/D converter 7, and the sample and hold circuit 2 operates alternately with the first sample and hold circuit 1, and outputs an analog input signal to the A/D converter 7. a second sample and hold circuit that extracts and holds the input signal;
The first switch 3 is connected to the first sample and hold circuit 1, the second switch 4 is connected to the second sample and hold circuit 2, and the switches 3 and 4 are connected to the first sample and hold circuit l and the second sample and hold circuit 1. The sample hold circuit 2 and the A/D converter 7 are alternately connected. Sample hold control circuit 6
→ first sample hole path 1 and first switch 3
, a second sample hold circuit 2 and a second switch 4
Control is performed so that the connection is alternately switched and connected.

[Effect]

FIG. 2 shows a principle characteristic diagram of the sample-and-hold circuit of the present invention. In the figure, ■ is the first sample hold circuit 1
■ is the output waveform of the second sample and hold circuit 2, ■ is the on-off signal of the first switch 3, ■ is the output waveform of the second
On/off signal of switch 4, ■ is A/D converter 7
The input waveform to is shown.

If the sample and hold control circuit 6 controls switching so that the first sample and hold circuit 1 and the second sample and hold circuit 2 operate alternately, the output waveforms of ■ and ■ are sent out alternately in the sample mode and the hold mode. be done. Therefore, the sample-and-hold control circuit 6 controls the on/off state of the switches 3 and 4 so that only the hold modes of the output waveforms (1) and (2) are taken out. When the ON signals of ■ and ■ are on, the hold mode state is extracted from the output waveforms of ■ and ■. The input waveform (2) to the A/D converter 7 is manually generated by combining the output waveform (2) and the hold mode portion of the output waveform (2). That is, in the manual waveform (2), if the switch switching timing is ignored, most of the sample mode portions of the output waveforms (2) and (4) are erased, and a continuous hold mode waveform is input to the A/D converter 7.

〔Example〕

A circuit configuration diagram of an embodiment of the present invention is shown in FIG.

In the figure, 1.2 is a sample hold circuit, 3°4 is a changeover switch, 6 is a control unit, 7 is an A/D converter, and 8
9 indicates a control switch for the sample and hold circuit 1, and 9 indicates a control switch for the sample and hold circuit 2.

Control signals for switches 8, 3, 9.4 are A and B.

C and D, and the conversion start signal of the A/D converter 7 is E, and by sending these signals A, B, C, D, and E from the control unit 6 as switching control signals, the A/D converter 7 is Continuously extracted sampling signals can be inserted.

A timing chart of the embodiment is shown in FIG.

In the figure, A is a control signal to the switch date, B is a control signal to switch 3, C is a control signal to switch 9, D is a control signal to switch 4, and E is a conversion start to A/D converter 7. As a signal, SH1 indicates the output mode of the sample-and-hold circuit 1, SH2 indicates the output mode of the sample-and-hold circuit 2, and AD indicates the input mode to the A/D converter 7.

Depending on the switching control signal from the control unit 6, switches 8 and 9 are operated alternately, switches 3 and 4 are operated alternately, switches 8 and 4 are operated simultaneously, and switches 9 and 3 are operated simultaneously. Operate. Conversion start signal E to A/D converter 7 at the same time as switch signal switching
is sent, but the start of conversion is delayed by the time t necessary for switching the switch.

When the switch 8 is open and the switch 3 is connected, the hold signal voltage stored in the capacitor is sent out from the sample and hold circuit 1, but at that time, the switch 4 of the sample and hold circuit 2 is opened. Therefore, no signal is sent out from the sample and hold circuit 2.

Next, when switch 8 of sample and hold circuit 1 is connected and switch 3 is open, sample and hold circuit 1
Although no signal is sent out from the sample-and-hold circuit 2, since the switch 9 of the sample-and-hold circuit 2 is open and the switch 4 is connected at that time, the hold signal voltage stored in the capacitor is sent out from the sample-and-hold circuit 2. Therefore, the hold signal voltages stored in the respective capacitors are alternately sent from the sample and hold circuits 1 and 2 to the A/D converter 7. At this time, the switching time t of the switch
Since the A/D converter 7 starts conversion after a certain delay, the settling time of the converter due to switching of the hold signal voltage is only delayed by the switching time t. The connection state of the switches in the circuit diagram of the embodiment shown in FIG. 3 shows the state when the hold mode signal is being sent from the sample and hold circuit 2.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is a principle characteristic diagram of the invention, Fig. 3 is a circuit diagram of the embodiment, Fig. 4 is a timing chart of the embodiment, and Fig. 5 is a diagram of the conventional example. The circuit configuration diagram and FIG. 6 show a principle characteristic diagram of a conventional example. In the figure, 1, 2.11 are sample and hold circuits, 3
, 4, 8, 9.13 are switches, 5 is an inverter, 6 is a sample and hold control circuit, 7.12 is an A/D converter, 14 is a capacitor, and 15 is a buffer amplifier. (Effects of the Invention) According to the present invention, the settling time from hold mode to sample mode is almost negligible, the transition time from one hold mode to the next hold mode is shortened, and the speed of analog/digital conversion in continuous sampling is increased. I can figure it out.

Claims (1)

[Claims] In a sample and hold circuit connected before an analog/digital converter, the first sample and hold circuit (1) extracts and holds an analog input signal in the analog/digital converter (7);
Consisting of the first sample and hold circuit (1) and a second sample and hold circuit (2) that operates alternately, the first sample and hold circuit (1) and the second sample and hold circuit (2). A first switch (3) and a second switch alternately connecting the analog/digital converter (7)
a switch (4), the first sample hold circuit (1) and the first switch (3), the second sample hold circuit (2) and the second switch (4), A double sample and hold circuit characterized in that switching is controlled alternately by a sample and hold control circuit (6).