JPH02276313A - Variable data generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a variable data generation device, and particularly to one that can increase or decrease data using a small number of change amount setting operators, and can immediately set a predetermined value. .

[Prior art]

2. Description of the Related Art Conventionally, devices have been proposed in which data output can be freely increased or decreased by operating an external operator.

This is disclosed, for example, in Japanese Patent Application Laid-Open No. 56-104545, which discloses a configuration in which the output frequency is varied by increasing/decreasing the division ratio of a programmable frequency divider. The external controls consist of a first control that changes the output frequency so as to increase it, and a second control that changes the output frequency in the direction of decrease. Data can be changed accurately with a simple configuration.

[Problems with conventional technology]

However, when attempting to set the data to the data before being varied by the operator, that is, to a reference value or a frequently used predetermined value, a dedicated switch must be provided to immediately return to these values. It is also possible to return to the original value by using two more operators, but this operation takes a very long time.

[Purpose of the invention]

The present invention allows data to be transferred without increasing the number of switches.
It is also an object of the present invention to enable instant setting of a desired value with a simple operation.

[Key points of the invention]

In order to achieve the above object, the present invention detects that a first operator that changes data in the increasing direction and a second operator that changes data in the decreasing direction are operated simultaneously. The present invention is characterized in that it includes a signal generating means that outputs a signal to be set to a predetermined value, and further includes a control means that variably controls other data based on this data.

〔Example〕

FIG. 1 is a main block diagram of an electronic musical instrument to which a variable data generator according to the present invention is applied. In the figure, 1 is a frequency generator, and the output of this frequency generator 1 is input to a frequency divider 2. After the frequency divider 2 divides the signal from the frequency generator 1 to 1/788, the phase comparator (P, D,)
Input at one end of 3. The output of this phase comparator 3 is passed through a low pass filter (LPF) 4 and a voltage controlled oscillator (VC
O) 5, input to the frequency divider 6.7, respectively "/2.1/
The frequency is divided into 3. The output of the frequency divider 6 is input to a programmable divider 8 to determine the frequency division ratio.

The frequency division ratio of this programmable divider 8 is specified by the tuning data generator 9, and the first operator 10 for increasing the tuning value and the second operator 11 for decreasing the tuning value are used. This is done through suppression operations. Further, the output of the programmable divider 8 is input to the other end of the phase comparator 3. Therefore, the phase comparator 3, low-pass filter 4, voltage-controlled oscillator 5, frequency divider 6, and programmable divider 8 constitute a PLL 12.

On the other hand, the output of this PLL 12 is inputted to the CLK terminal of the musical tone generating section 13 via the frequency divider 7, and is input to the CLK terminal of the musical tone generating section 13.
This becomes the reference clock for No. 3. Further, in this musical tone creation section 13, a key switch section 14 (No. 9) having switches for specifying the type of key and rhythm, etc. inputs input via a CPU (comprised of a central control unit, two microprocessors, etc.) 15. There is. Then, the musical tone creation section 13 creates a musical tone based on the reference clock from the PLL 12 via the frequency divider 7, that is, at a desired tuning value, and outputs the sound through an amplifier and a speaker (not shown). Ru.

Next, FIG. 2 shows a specific circuit of the tuning data generation section 9 corresponding to the variable data generation device. One end of the first operator 10 and the second operator 11 is each grounded, while the other end is supplied with a voltage V via resistors R1 and R2, respectively. The first and second operators 10.11 are also an inverter 16.17, a one-shot multi 18.19
, and are input to one end of AND gates 20 and 21, respectively.

The output of the one-shot multi 18.19 is passed through the inverter 22.23 to the AND gate 20.21.
Input each at the other end. And this and gate 20
．． The outputs of 21 are input to the counter section 30 as count UP1 count down signals through AND gates 24, 25, OR gates 26, 27, and AND gates 28, 29, respectively. On the other hand, the output of the oscillator 31 is input to the other end of the AND gate 24.25. In addition, the above first,
The output from the second operator 10.11 is the differentiating circuit 32.
33, and the first and second operators 10111
Output occurs only at the moment when is pressed. The outputs of the differentiating circuits 32 and 33 are input to the other ends of the OR gates 26 and 27, respectively. In addition, the voltage V passing through the resistors R1 and R2 is input to the AND gate 36 via the inverters 34 and 35, and the output of the AND gate 36 is a RESET signal that sets the counter section 30 to a predetermined value. Enter as . The outputs of the counter section 30 are input to the Nantes gates 37 and 38, respectively, and are further input to the Nantes gates 37 and 38.
8. Input each to the other end of 29. Here, when the value of the upper counter section 30 reaches a desired maximum value, the Nant gate 37 outputs "0", closes the AND gate 28, and stops the UP operation of the counter section 30. Further, when the output of the Nant gate 38 reaches "0" when the value of the counter section 30 reaches a desired minimum value, the AND gate 29 is closed, and the count of the counter section 30 becomes "0".
Stop the wn operation. On the other hand, the output of the counter section 30 is input to a decoder 39, decoded, and input to the programmable divider 8.

Next, the operation of the above embodiment will be explained.

Oscillation from the frequency generator 1 above, frequency 4.9488
48 (MH2) is frequency-divided by frequency divider 2 to 1/768 and input to PLL 12. And this PLL
The frequency dividing ratio of the programmable divider 8 in the programmable divider 12 is determined by data from the tuning data generating section 9, and the output from the PLL 12 is inputted to the tone generating section 13 via the frequency divider 7. At this time, when the frequency division ratio of the programmable divider 8 is 1/1152,
The signal from the frequency divider 7 is 4.94E384 (MH2
), and A4=442 (H2) is set.

At this time, when the second operator 11 is pressed, a one-shot signal is output from the differential circuit 33 and passed through the OR gate 27.
It is input to one end of the AND gate 29. Here, the output of the Nant gate 38 is "1" because the counter section 30 has not reached the minimum value, and the AND gate 29 is closed.

Therefore, the signal output from the OR gate 27 passes through the AND gate 29 and causes the count value of the counter section 3° to decrease by 1. Then, the decoder 39 decodes the frequency division ratio of the programmable divider 8 to 1/11.
Set it to 51. At this time, the output signal of the frequency divider 7 is attenuated by 4294 (Hz), and the output signal of the frequency divider 7 is attenuated by 4294 (Hz), and the output signal of the frequency divider 7 is attenuated by 4294 (Hz).
Enter. As a result, A4=441.6 (Hz), which is about 1.5 cents lower.

When the second operator 11 is pressed again, the above operation is repeated, and the output signal of the frequency divider 7 becomes 4294 (H
z), resulting in A4 = 441.2 (Hz), which is about 1.5 cents lower.

Here, it is assumed that the second operator 11 is continued to be pressed.

First, a single signal is output from the differentiating circuit 33, and the OR gate 2
7, and the count value of the counter section 30 is decremented by 1 via the AND gate 29.

Approximately 0.5 seconds later, the output from the Q terminal of the one-shot multi 19 becomes "0", and the signal inverted by the inverter 23 is input to one end of the AND gate 21 (7). The other end of this AND gate 21 is connected to the inverter 17
The “1” signal output via the is input. Then,
A "1" signal is output from the AND gate 21, and the AND gate 25 is closed. Therefore, approximately 10 (
Hz) is outputted, and inputted to the counter section 3o via the AND gate 25, the OR gate 27, and the AND gate 29, and is counted.
n operations are performed. Then, it is decoded by the decoder 39, and the frequency division ratio of the programmable divider 8 is changed to attenuate the tuning value. Note that when the preset count value is reached, the output signal from the Nant gate 38 becomes "0", the AND gate 29 is closed, and the count down operation of the counter section 30 is stopped. Therefore, the tuning value is set so that it does not go below a certain value.

The operation of the first operator 10 is exactly the same as that of the second operator 11, and when it is pressed once, the count value of the counter section 30 is incremented by 1, and it is kept pressed for 0.5 seconds. The count value is continuously incremented. When the preset value is reached, the UP operation is stopped.

On the other hand, the first and second operators 10.11 are pressed simultaneously. The output of inverter 34.35 becomes "61",
A signal is generated from AND gate 36. This signal is
This is a signal for resetting the counter section 3o. Therefore, the value of the counter section 30 is reset to a predetermined value.

At this time, the output of the counter section 30 is decoded by the decoder 39, and the frequency division ratio of the programmable divider 8 is set to 1/1152. In other words, the first and second
By pressing the operators 10 and 11 at the same time, the tuning value is instantly set to A4=442 (H2).

As described above, after tuning, by setting a desired tone using the key switch section 14 and pressing a desired key, the corresponding tone code and key code are outputted via the CPU 15. The musical tone generating section 13 outputs a musical tone signal corresponding to the pitch of the pressed key with the desired tone color and based on the set tuning value, and outputs a musical tone signal corresponding to the pitch of the pressed key, and sends it to the speaker 5 via an amplifier (not shown). ．． - Make the sound emit by force.

In the embodiment described above, since the clock is obtained using a PLL, there is an excellent effect that a highly accurate and highly stable tuning value can be obtained.

Furthermore, the clock frequency can be easily varied by simply changing the frequency division ratio of the programmable divider.

In the above embodiment, the variable data generator of the present invention is applied to tuning control of an electronic musical instrument.
It can be similarly applied to other variable frequency generators, and has extremely high versatility.

〔Effect of the invention〕

The variable data generator of the present invention is provided with a first operator that increases data and a second operator that decreases data, and by simultaneously operating the first and second operators,
Since the above data can be set to a predetermined value and other data can be variably controlled based on this variable or set data, the value of the output data can be freely controlled, and the data can be changed from any value. However, since it can be set to a specific value instantaneously, the operation becomes extremely easy to variably control the value of the above-mentioned function data, and there is no need to install additional switches.

[Brief explanation of drawings]

FIG. 1 is a main block diagram of an electronic musical instrument to which the present invention is applied, and FIG. 2 is a detailed diagram of a tuning data generator that generates a basic clock for driving the electronic musical instrument, which corresponds to the variable data generator of the present invention. This is a typical circuit diagram. 8... Programmable divider, 9... Tuning data generation section, 10... First operator, 11... Second operator, 12... PLL1 13... Musical tone creation section, 18 .19...One-shot multi, 30...Counter section, 32.33...Differential circuit, 39...Decoder. Patent applicant Casio Computer Co., Ltd. 2m

Claims (2)

[Claims] (1) A storage means in which stored data is stored, a first operator for changing the stored data stored in the storage means in the direction of increasing it, and a first operator for changing the stored data stored in the storage means in the direction of decreasing it. generating a signal for detecting that a second operator to be changed and the first and second operators are operated simultaneously and outputting a signal to the storage means to set the stored data in the storage means to a predetermined value; A variable data generation device comprising: means; and control means for variably controlling other data based on the data stored in the storage means. (2) The storage means includes variable range setting means that allows the first and second operators to increase or decrease the value only when the value of the stored data is within a certain range. Variable data generator described in Section 1.