JPH02276338A - Cyclic digital information transmission/reception equipment - Google Patents

Abstract

PURPOSE:To receive information without taking the classification of the transmission format in a system into consideration by providing the detecting function of plural synchronous patterns and providing a function by which an equipment is operated in the reception mode of the transmission format corresponding to the detected synchronizing pattern. CONSTITUTION:A serial signal 13 obtained by demodulation in the preceding stage is inputted to a microprocessor unit 11 synchronously with the input timing signal 14 of a timing extracting circuit 12, and serial/parallel conversion, parity detection, inverted continuous transmission collation, etc., are performed in the unit 11 by the internal firmward control. In the microprocessor unit 11, the synchronous pattern peculiar to each preliminarily set system is used to perform respective processings of synchronous pattern detection, system discrimination, and operation mode setting, and the reception control operation is performed in accordance with the corresponding format.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a cyclic digital information transmission/reception device, and more specifically, to a cyclic digital information transmission/reception device for receiving information cyclically and sequentially transmitted in a system for transmitting digital information. The present invention relates to a cyclic digital information transmission/reception device used.

[Prior Art] A cyclic digital information transmitting/receiving device is a receiving device that receives information that is cyclically and sequentially transmitted in a system that time-division multiplexes and transmits information following a synchronization word.

Conventionally, cyclic digital information transmission/reception devices in this type of system have been designed taking into consideration the types of transmission formants in the system, and have been designed to accommodate each format depending on the number of bits in one word. It is common to adopt a configuration in which a receiving section is prepared.

That is, conventionally, in the transmission format of a cyclic digital information transmitting/receiving device, the number of bits of a word is 40 pinto, 44 bit, 60 bit, etc., depending on the difference in the system to be applied. When there are differences in the number of bits of words and data format configurations, it is possible to create a cyclic digital information transmission receiving device suitable for the desired method by preparing a receiving section compatible with each method. I'm trying to get it.

As will be described later, FIG. 4 is a format diagram for explaining an embodiment of the present invention, and also shows the above-described difference in the number of bits in one word. That is, in the case of a 40-bit system word structure as shown in FIG.
A frame as shown in Figure (a) will be constructed and transmitted.

The 44-bit word structure and 64-bit word structure shown in FIGS. 4(c) and 4(d) also follow this, and one word consists of 44 bits and 64 bits, respectively. In this way, when the number of words per bit is 40 bits, 44 bits, 64 bits, etc., a receiving section suitable for each system must be prepared.

[Problems to be Solved by the Invention] However, with the conventional methods, there is a difficulty in compatibility when trying to receive any of a plurality of mutually different transmission formats. The inconvenience becomes even greater in cases where there is a mixture of methods.

That is, in the above-mentioned conventional cyclic digital information transmission receiving device, as mentioned above, the device is generally configured so that a receiving section is prepared for each method depending on the number of bits of one word, or , the device is configured by preparing a receiving section with desired settings for one type of receiving section that supports multiple methods; therefore, multiple methods can coexist in one system. If you use the former method, you must prepare a receiving unit for each, and if you use the latter method, in other words, if you use a receiving unit that supports multiple methods, you must configure settings for each line. No.

As described above, in any case, the system using a plurality of formant configurations cannot be said to have sufficient compatibility.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cyclic digital information transmission/reception apparatus that eliminates the above-mentioned conventional drawbacks and is not affected by differences in data format configurations.

[Means to solve the problem]

The cyclic digital information transmission receiving device of the present invention includes a reception control section at the next stage of the demodulator, and the output signal of the demodulator is input to the reception control section, and the reception control section also inputs a plurality of synchronization patterns. It is characterized by having a detectable synchronization pattern detection function and a reception function in a plurality of transmission formats corresponding to the synchronization patterns detected by the synchronization pattern detection function.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of the main parts of a reception control section in a cyclic digital information transmission/reception apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of the configuration of the cyclic digital information transmission/reception apparatus. .

Generally, a cyclic digital information transmission/reception device can be represented by the block diagram shown in FIG.

The cyclic digital information transmission and reception device shown in FIG.
As shown in the figure, a demodulator (DEM) 21 and a demodulator 21
A reception control unit (S/P), a central processing unit (CPU) 23, and an external interface unit (1/F) arranged next to the
24.

The operation in the above configuration is basically as follows. That is, in FIG. 2, the serial signal demodulated by the demodulator 21 is input to the reception controller 22, and the serial signal is demodulated by the demodulator 21.
performs serial-to-parallel conversion, synchronization establishment, parity verification, reverse transport verification, etc., and passes the signal to the next stage central processing unit 23.

A block diagram of the main parts of this reception control section 22 is shown in FIG.

In this embodiment, as shown in FIG. 1, a timing extraction circuit (TIMING) 12 is provided with a serial signal 13 which is a demodulated output signal from a previous stage, and a timing extraction circuit (TIMING) 12 is supplied with a serial signal 13 and an input timing signal from the timing extraction circuit 12. 1
Microprocessor unit (MPU) supplied with 4
11 is provided, and the output of the microprocessor unit 11 is sent out as the next stage output signal 15.

As described above, the cyclic digital information transmission receiving device of this embodiment uses a microprocessor in the configuration of the reception control section located at the next stage of the demodulator, and is capable of supporting systems with multiple format configurations through its firmware control. The microprocessor unit 11 shown in FIG. 2 realizes a function of detecting a plurality of synchronization patterns and a reception function of a plurality of transmission formats corresponding to the synchronization patterns detected by the synchronization pattern detection function. I have to.

That is, it has a plurality of synchronization pattern detection functions, and determines the operation mode of the reception control function corresponding to the synchronization pattern detected by the synchronization pattern detection functions, under firmware control. Here, the reception control function generally refers to the aforementioned serial/parallel conversion of signals in the cyclic digital information transmission receiver, establishment of synchronization, parity verification, reverse transport verification, etc. The operating mode of the control function is selectively and automatically set according to the synchronization pattern.

Specifically, the operation mode is set according to a program process, an example of which is shown in FIG. 3, which will be described later. Control is executed to enable reception control operations according to each format.

A more specific explanation will be given below with reference to FIGS. 3 and 4.

FIG. 3 is a flowchart of a part of the initial processing in the firmware of the reception control unit in the cyclic digital information transmission/reception device according to the present invention, and FIG. 4 is a format diagram showing an example of the format as already mentioned. be.

In FIG. 1, the serial signal 13 obtained by demodulating in the previous stage
is input to the microprocessor unit 11 in synchronization with the input timing signal 14 from the timing extraction circuit 12, where serial/parallel conversion, parity detection, inverse transport verification, etc. are performed under internal firmware control.

To execute such reception control functions, the microprocessor unit 11 utilizes preset synchronization patterns specific to each method, and performs synchronization pattern detection, method discrimination, and operation mode setting (steps 301 to 3) as shown in FIG. 303
) to ensure that the reception control operation follows the corresponding format.

The synchronization pattern used is selected to be a bit arrangement that does not appear in other information words, and an example of this synchronization pattern is shown in FIG. As shown in FIG. 4, the synchronization pattern constitutes a unique synchronization pattern by inserting N r□ between two binary "1"s.

The number of "0"s to be inserted is different for each system, and in the 40-bit system there are 22 (Figure 4(b) (i)
)), 42 in the 44-bit system (Figure 4(c)(i)
), 62 in the 64-bit system (Figure 4(d)(i))
It is.

The microprocessor unit 11 identifies the method based on the synchronization pattern unique to each method, and determines the operation mode by internally registering the type of synchronization pattern detected first. At step 303, once the operation mode is determined, the reception control operation follows each format.

In this way, in a cyclic digital information transmission/reception device, the output signal is input to the next stage of the demodulator, and the synchronization pattern detection function for multiple synchronization patterns and the synchronization pattern detected by this synchronization pattern detection function are supported. When the component includes a reception control unit that has a reception function in multiple transmission formats, it operates in the reception mode of the transmission format corresponding to the detected synchronization pattern as follows, even if one system is configured as shown in Figure 4 ( Even when the systems b) to (d) are mixed, it is possible to receive any transmission format.

That is, when a system to which the cyclic digital information transmission/reception device of the above configuration is applied is started up, the microprocessor unit 11 inputs the serial signal 13 bit by bit, and each time it inputs the bit array ( The synchronization pattern is compared with an internally registered synchronization pattern (a unique pattern). As mentioned above, the microprocessor unit 11 determines the operating mode by internally registering the type of synchronization pattern detected first, and the operating mode is determined once according to the process shown in FIG. If so, the reception control operation will be performed in accordance with each format, and therefore it is possible to perform control so that reception can be easily performed even in a plurality of transmission formats, and high compatibility can be obtained.

[Effects of the Invention] As explained above, according to the present invention, by having the function of detecting a plurality of synchronization patterns and operating in the reception mode of the transmission format corresponding to the synchronization patterns, the system can be improved. This has the effect of making it possible to receive any transmission format without considering the type of transmission format.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main part of a reception control section in a cyclic digital information transmission/reception device according to an embodiment of the present invention, FIG. 2 is a block diagram of the configuration of the cyclic digital information transmission/reception device, and FIG. FIG. 4 is a flowchart of a part of the initial processing in the firmware of the reception control unit of the cyclic digital information transmission and reception apparatus of this embodiment. FIG. 4 is a format diagram showing an example of a transmission format for explaining the present invention. 11...Microprocessor unit 12...
... Timing extraction circuit 13 ... Serial signal 14 ... Input timing signal 15 ... Next stage output signal 21 ... Demodulation section 22 ... Reception control section 23 ... Central processing section 24 ... External interface section Fig.

Claims (1)

[Claims] (1) A reception control unit is provided at the next stage of the demodulator, and the output signal of the demodulator is input to the reception control unit, and the reception control unit has a synchronization pattern detection function that can detect multiple synchronization patterns, and A cyclic digital information transmission/reception device characterized by having a receiving function in a plurality of transmission formats corresponding to a synchronization pattern detected by a synchronization pattern detection function.