JPH0227647Y2 - - Google Patents

Description

[Detailed description of the invention] (Field of industrial application) This invention processes PCM (Pulse Code Modulation) digital signal data by determining whether it is correct (OK) or incorrect (NG). This invention relates to a data judgment circuit.

(Prior art and its problems) Generally, PCM data converted from an analog signal to a digital signal by PCM is, for example,
Redundant data such as music signals recorded on magnetic tape (data that has extra bits such as error correction bits in addition to information bits), and when demodulating this data, Errors may occur in data due to dust, defects in magnetic materials, or some cause in the data processing process (interference between symbols, noise, etc.).

In response to such data errors, it is necessary to interrupt (mute) the transmission of the error data using a mute circuit so that the error data is always set to zero and only correct data is transmitted.

By the way, among the data errors mentioned above, for single and short-term data errors that sometimes occur,
If the data is muted each time, serious problems may occur, such as the demodulated data being completely different from the original data before modulation. Therefore, it is necessary to operate the mute circuit to mute data only when data errors occur continuously.

In addition, for the occasional single and short-term data errors mentioned above, data pre-interpolation (a method of replacing error data with the data immediately before it)
It is possible to perform error correction by performing data correction processing using methods such as or intermediate value interpolation (a method of replacing error data with the average value of data before and after it). In particular, data obtained by analog/digital conversion of a music signal has a high correlation between samples, so error correction using the above-mentioned pre-interpolation, intermediate value interpolation, etc. is effective.

In addition, it is difficult to interpolate error data that occurs continuously, and there is a high possibility that there will be a significant discrepancy with the original signal, so data transmission is interrupted (mute). Must.

Therefore, when single-shot and short-term data errors occur from time to time, especially for input data such as music signals where each sample is highly correlated, there is no need to mute the data, and instead pre-interpolate the data. It is sufficient to correct the error using a method such as or intermediate value interpolation; conversely, muting the data will cause serious problems such as not being able to obtain correct demodulated data as described above.

Also, if data errors occur continuously, if error correction is performed using interpolation, the interpolated data will continue, resulting in data discrepancies, so in this case, the data must be muted. .

In this way, to determine whether data is correct (OK) or incorrect (NG), it is necessary to determine the continuity of the error data (whether it is continuous error data or single-shot or short-time error data), and then select OK or NG.
It was necessary to output the final judgment of NG.

In particular, when determining data such as music signal data converted to PCM data, even if some error data continues for a long time, the influence of demodulation errors is small, but rather the influence of noise generation due to data interruption is large. Judgment that takes into account the continuity of the error data described above is effective.

However, conventional digital integration circuits for data judgment simply integrate correct data or error data to make data judgments.

In addition, in magnetic recording and reproducing devices (PCM recorders) that record and reproduce music signals converted to PCM data on magnetic tape, jitters (signal time axis directional fluctuations),
Memory (Random Access Memory (RAM)) is used to correct errors in data. At this time, it is desirable to have a large jitter margin (margin) with as little memory capacity as possible.

Here, if the data on the memory is schematically expressed, it will be as shown in Figure 3. When data is written to the position indicated by diagonal lines in the approximate center of the memory area (the range indicated by the rectangle in the figure), the memory Both sides of the area {the area other than the area indicated by diagonal lines in the rectangle (white area)} serve as margins.

As shown in Figure 4a, when data is written outside the middle position of the memory area, the margin on one side of the memory area decreases, resulting in an underflow (overflow of lower digits) of the data in the memory. In this case, interrupt the data transmission, initialize the memory, and then
As shown in Figure 3, data must be rewritten to the center of the memory area and data transmission must begin again. Furthermore, when an overflow (overflow of upper digits) of data in the memory occurs, data transmission must be interrupted in the same way as above, and data transmission must be restarted after initialization.

Therefore, even if the data is OK, it is not known where in the memory it was written, so it is safer to initialize the memory once.

However, once the data is written to the central location of the memory area during initialization, the data becomes NG.
Therefore, data transmission must be interrupted. Eventually, the steady state will be reached and the data will be OK.
The state is now ready for data transmission.

As described above, once the memory is initialized, a state in which no data is transmitted continues, resulting in a problem that the timing until a steady state is reached and data is transmitted is delayed.

Therefore, in view of the above-mentioned conventional technology, the present invention is
The purpose of this invention is to provide a data judgment circuit that solves this problem.

(Means for solving the problem) In order to achieve the above purpose, the present invention
(A is the maximum count value, N is a natural number), it is an N-ary counter, and only while an error flag indicating a data error is supplied, the number of word clocks corresponding to the data unit is counted and the count value is set. an NG counter 1 that outputs a carry when the maximum count value A is reached, and stops the carry output when the error flag is no longer supplied;
It is preset to B-M1 (B is the maximum count value, M1 is a natural number, where M1>N) and is an M1-based counter, and only while the carry output from the NG counter is stopped, the number of the word clocks is counted. a first determination counter 2 which outputs a carry when the count value reaches the maximum count value B and stops the carry output when a carry output is supplied from the NG counter; Count value, M2 is a natural number, however, M2>M1)
The counter is preset to M2, and only while the carry output from the NG counter is stopped, it counts the number of word clocks, and when the count value reaches the maximum count value C, it outputs a carry. The above by the carry output
a second judgment counter 4 that sets the NG counter to a preset value smaller than the preset value and stops the carry output when the carry output is supplied from the NG counter; and DL (D is the maximum count value;
L is a natural number, but is preset to M1>L),
The counter is an L-base counter, and only while the carry output from the NG counter is stopped, it counts the number of word clocks, and when the count value reaches the maximum count value D, it outputs a carry;
It consists of an initialization setting pulse generation counter 3 that stops the carry output when the carry output is supplied from the NG counter, and a NAND output of the carry output of the first judgment counter and the carry output of the second judgment counter. is output as the final judgment result of whether the data is correct or incorrect, and the first
The present invention provides a data judgment circuit characterized in that the exclusive OR output of the carry output of the judgment counter and the carry output of the initialization setting pulse generation counter is output as the initialization setting pulse.

(Embodiment) An embodiment of the data judgment circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the data judgment circuit according to the present invention, and FIG. 2 is a time chart showing changes in signals at each point in the circuit of FIG.

In FIG. 1, the NG counter 1 is
(A is the maximum count value, N is a natural number), it is an N-ary counter, and the load input terminal
Error flag indicating data error in LD {2nd
The waveform shown in Figure b (H level for data, L level for OK) is supplied to the clock terminal CK, and a word clock corresponding to the data unit {waveform shown in Figure 2 a} is supplied to the clock terminal CK.
is supplied, the number of word clocks is counted, and when the count value reaches the maximum count value A, a carry {waveform shown in FIG. 2 c} is output from the carry output terminal CA.

The carry output terminal CA of the NG counter 1 is connected to the enable terminal EN of the NG counter 1 and the first, second, and third OK counters 2 and 3 through the inverter 6.
It is connected to each load input terminal LD of No. 3 and No. 4, respectively. Note that the counter operates or stops depending on the input state to the enable terminal EN.

The first OK counter 2 is preset to B-M1 (B is the maximum count value, M1 is a natural number, where M1>N), is an M1-based counter, and is output from the NG counter 1 to the load input terminal LD. The inverted signal {waveform shown in Figure 2 d} of the carry {c} is supplied, and the word clock {a} is supplied to the clock terminal CK.
is supplied, the number of word clocks is counted, and when the count value reaches the maximum count value B, a carry {waveform shown in FIG. 2 e} is output from the carry output terminal CA.

Carry output terminal CA of first OK counter 2
are connected to one input terminal of the NAND circuit 7, and to one input terminal of the AND circuit 9 and one input terminal of the exclusive OR circuit (exclusive OR circuit) 5 via the inverter 8. be done. Furthermore, the output terminal of the AND circuit 9 is connected to the enable terminal EN of the first OK counter 2.

The third OK counter 4 is preset to C-M2 (C is the maximum count value, M2 is a natural number, where M2>M1), is an M2-based counter, and is output from the NG counter 1 to the load input terminal LD. The inverted signal {d} of the carry {c} is supplied, the word clock {a} is supplied to the clock terminal CK,
When the number of word clocks is counted and the count value reaches the maximum count value C, the carry output terminal CA
A carry {waveform shown in FIG. 2 g} is output.

Carry output terminal CA of third OK counter 4
is connected to the other input terminal of the NAND circuit 7, and is connected to the other input terminal of the AND circuit 9 via the inverter 11. Furthermore, the output terminal of the NAND circuit 7 is connected to the enable terminal EN of the third OK counter 4 and the preset input terminal of the NG counter 1, respectively.

Then, from the output terminal of the NAND circuit 7, the final judgment output result of whether the data is OK or NG (waveform in Figure 2 h; H level when NG, L level when OK) is output. be done.

The second OK counter 3 (counter for initializing pulse generation) is preset to DL (D is the maximum count value, L is a natural number, M1>L), is an L-base counter, and has a load input. terminal
The inverted signal {d} of the carry {c} output from the NG counter 1 is supplied to the LD, the word clock {a} is supplied to the clock terminal CK, the number of word clocks is counted, and the count value reaches the maximum count value D. Then, a carry {waveform shown in FIG. 2 f} is output from the carry output terminal CA.

Carry output terminal CA of second OK counter 3
is connected to the enable terminal EN of the second OK counter 3 and the exclusive terminal via the inverter 10.
They are respectively connected to the other input terminals of the OR circuit 5.

An initialization pulse (initialization setting pulse) {waveform shown in FIG. 2 i} is output from the output terminal of the exclusive OR circuit 5.

The operation of the circuit of the present invention having the above-mentioned configuration will be explained below.

When the power is turned on as shown in the time chart in Fig. 2, at the first rise of the word clock (waveform in Fig. 2 a) immediately after the power is turned on, the NG counter 1 is loaded and the preset values A-N are read. Load NG counter 1].

When the error flag (H level) {waveform shown in Figure 2 b} is supplied to the load input terminal LD of the NG counter 1, and the load input terminal LD goes to the H level, the NG counter 1 records the number of error data during this H level. Count the number of word clocks corresponding to
When the error flag (H level) continues for a long time (the error continues to occur) like when the power is turned on, and the word clock count value reaches the maximum count value A, a carry signal is output from the carry output terminal CA (waveform in Figure 2 c). output and at the same time stop counting. And this carry {c} (H level) is
It is held until the error flag {a} is no longer supplied (L level) and the load input terminal LD of the NG counter 1 becomes L level.

In addition, if the error flag (H level) is short and the load input terminal LD becomes L level before the word clock count value reaches the maximum count value A (when no errors occur), the carry output is Not done.

When the error flag is no longer supplied to the load input terminal LD of NG counter 1 (L level) and the load input terminal LD becomes L level, the carry output {c} stops (becomes L level) at the next rising edge of the word clock. ), NG counter 1 is loaded and the preset values AN are read [LOAD OF NG COUNTER 1]. In this state, when the error flag (H level) is supplied as described above, counting of the number of word clocks is started.

The carry output {c} of the NG counter 1 is inverted by the inverter 6, {the waveform shown in FIG.
The signal is supplied to each load input terminal LD of the third OK counters 2, 3, and 4, respectively.

When the inverted signal {d} of the carry output {c} of the NG counter 1 goes to L level and the load input terminal LD of the first OK counter 2 goes to L level, the first OK counter 2 is loaded and the preset value is set. B-M1 is read [load of first OK counter 2].

Similarly, the inverted signal {d} of the carry output {c} of the NG counter 1 becomes L level, and the second
When each load input terminal LD of the OK counter 3 and the third OK counter 4 becomes L level,
Second OK counter 3 and third OK counter 4
are loaded respectively, and the preset values D-L and C-M2 are read respectively [second OK]
Loading counter 3 and third OK counter 4].

When the carry output {c} of the NG counter 1 stops (becomes L level) and its inverted signal {d} becomes H level, the first OK counter 2 counts the number of word clocks during this H level. However, when the count value of the word clock reaches the maximum count value B, a carry {waveform shown in FIG. 2 e} is output from the carry output terminal CA, and at the same time, counting is stopped. And this carry {e} (H level) is
Carry {c} (H level) from NG counter 1
is output, its inverted signal {d} becomes L level, and the load input terminal LD of the first OK counter 2
It is held until it reaches L level.

Also, in parallel with the above operation, the carry output {c} of NG counter 1 stops (becomes L level),
When the inverted signal {d} becomes H level, this H
During the level, the second OK counter 3 and the third
The OK counter 4 counts the number of word clocks, and when the word clock count reaches the maximum count value D, C, a carry is output from each carry output terminal CA {waveforms f and g in FIG. 2}
output and at the same time stop counting. And this carry {f, g} (H level) is
Carry {c} (H level) from NG counter 1
is output, its inverted signal {d} goes to L level, and is held until each load input terminal LD of the second OK counter 3 and third OK counter 4 goes to L level.

The carry output {e} of the first OK counter 2 is supplied to one input terminal of the NAND circuit 7, and the third
The carry output {g} of the OK counter 4 is supplied to the other input terminal of the NAND circuit 7. first
When the carry {e} of the OK counter 2 and the carry {g} of the third OK counter 4 are both output (reaching H level), the output {h} of the NAND circuit 7 becomes L level (data OK). ),
Until then, it will be at H level (determined as data NG).

The output {h} of this NAND circuit 7 is supplied to the enable terminal EN of the third OK counter 4, while being fed back to the preset input terminal of the NG counter 1. A new preset value is set in the NG counter 1 when the output {h} changes from the H level (NG) to the L level (OK). For example, a new preset value is set by inputting a feedback signal as a select signal to a select terminal of a data selector (not shown).

Furthermore, the output {h} of the NAND circuit 7 is
The final judgment output result of determining whether it is OK or NG {waveform in Figure 2h; H level when NG;
When OK, the level is L.

In addition, when the output {h} of the NAND circuit 7, which is the final judgment output result of the above data OK/NG, is NG at H level, a miute circuit (not shown) is operated to interrupt data transmission (miyuto). However, on the other hand,
When the L level is OK, the mute circuit (not shown)
data transmission without operating.

When the output {h} of the NAND circuit 7 is fed back to the preset input terminal of the NG counter 1 (i.e.,
When setting a new preset value of the NG counter 1 from NG to OK, the preset value of the NG counter 1 is set smaller than the initial preset value.

As a result, even if the error flag (H level) continues for a while (i.e., the error continues to occur) when this is determined to be OK (when the output {h} of the NAND circuit 7 is at the L level), ), as the preset value becomes smaller, the period until the word clock count value reaches the preset value becomes longer, so it becomes difficult for carry to be output from NG counter 1, and therefore the time from NG to OK is reduced. period (i.e., the count value of the first OK counter 2 reaches the maximum count value B, and the third OK counter
Each time the period from OK to NG changes from NG to OK (period until the count value of counter 4 reaches the maximum count value C), the preset value of NG counter 1 is set smaller. Therefore, even if the error flag (H level) continues for a long time, the period in which the judgment of OK is maintained will be longer, and the process of OK → NG will be delayed.
It is possible to have a hysteresis characteristic from NG to OK.

Here, assuming that the preset value B-M1 of the first OK counter 2 and the preset value DL of the second OK counter 3 are the maximum count value B=D, M1
>L (in the case of Figure 2, the difference is one word clock), so the carry output {f} of the second OK counter 3 is one word clock with respect to the carry output {e} of the first OK counter 2. (becomes H level).

That is, for the purpose of generating an initialization pulse to be described later, the maximum count value B=D,
The preset value D-L of the second OK counter 3 is made smaller than the preset value B-M1 of the first OK counter 2 (in the case of FIG. 2, it is made smaller by one word clock), and the second OK counter 3 first
If you run it in parallel with OK counter 2,
earlier than the first OK counter 2 (in other words,
It is possible to output the carry (by shifting the time).

In connection with this, the carry output {e} of the first OK counter 2 is inverted via the inverter 8 and supplied to one input terminal of the exclusive OR circuit 5, and the carry output {e} of the second OK counter 3 is inverted and supplied to one input terminal of the exclusive OR circuit 5. Since the output {f} is inverted via the inverter 10 and supplied to the other input terminal of the exclusive OR circuit 5, an initialization pulse (initialization setting pulse) {th The waveform shown in Figure 2 i is output.

As a result, the error flag is no longer supplied (that is, the error no longer occurs), the carry output {c} of NG counter 1 stops (becomes L level), and this OK state with no error continues for a long time. , a carry is output from both the first OK counter 2 and the third OK counter 4, the output {h} of the NAND circuit 7 becomes L level, and the data
An initialization pulse can be generated before it is determined that it is OK.

Note that, assuming the maximum count value B=D, the second
The preset value DL of OK counter 3 is the first
If there is a difference of one word clock or more from the preset value B-M1 of OK counter 2, L>M1
But it's okay. However, in the case of L>M1, unless M2>L, the initialization pulse cannot be generated before it is determined that the data is OK as described above.

In this way, the exclusive OR circuit 5 uses the time difference in the carry output timing of each counter due to the difference in the preset values of the first OK counter 2 (or the third OK counter 4) and the second OK counter 3. data from the output terminal of
An initialization pulse (initialization setting pulse) {i} can be output before it is determined that it is OK.

Then, when the NG state where an error flag is supplied changes to the OK state where no error occurs (that is, the output {h} of the NAND circuit 7, which is the final judgment output result of data OK/NG, changes from the H level to the L level. (time) can always generate an initialization pulse.

Therefore, when the OK state is reached, all peripheral logic circuits such as memory are in the initialized state, so these peripheral circuits can be operated in an ideal state.

(Effects of the invention) As described above, according to the data judgment circuit of the invention, it is possible to judge an error (NG) only when the input error data continues, and output the final judgment. The duration of error data from (OK) to error (NG) is set longer each time it changes from NG to OK.
Even if the error data continues for a long time, the period in which the judgment of OK is maintained becomes longer, and the hysteresis characteristic of NG → OK can be provided for the process of OK → NG.
When judging the data of a music signal converted to PCM data, even if some error data continues for a long time, the influence of demodulation errors is small, but rather the influence of noise generation due to data interruption is large. It is valid.

Furthermore, according to the circuit of the present invention, an initialization setting pulse can be output before the final judgment of OK is output, and when the OK state is reached, all peripheral logic circuits such as memory are initialized. This allows these peripheral circuits to operate in an ideal state, and then initialization settings are performed after the state is OK, and data cannot be transferred once the state is NG and then the state is OK again. Compared to the case of transmission,
The state in which data transmission is interrupted can be shortened, and the delay until data transmission can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the data judgment circuit according to the present invention, FIG. 2 is a time chart showing changes in signals at each point of the circuit of FIG. 1, and FIG.
4 and 4 are diagrams schematically showing data on the memory. 1... NG counter, 2... First OK counter (first judgment counter), 3... Second OK counter (initialization setting pulse generation counter), 4
...Third OK counter (second judgment counter),
5... Exclusive OR circuit (exclusive OR circuit), 6.8, 10, 11... Inverter,
7...NAND circuit, 9...AND circuit.

Claims (1)

[Claims for Utility Model Registration] It is preset to A-N (A is the maximum count value, N is a natural number), is an N-ary counter, and is used in units of data only while an error flag indicating a data error is supplied. The number of corresponding word clocks is counted and the count value is the maximum count value A.
An NG counter that outputs a carry when the error flag is no longer supplied and stops the carry output when the error flag is no longer supplied, and B-M1 (B is the maximum count value, M1 is a natural number,
However, it is preset to M1>N) and is an M1-based counter, and only while the carry output from the NG counter is stopped, the number of word clocks is counted and the count value reaches the maximum count value B. a first judgment counter that outputs a carry signal and stops the carry output when the carry output is supplied from the NG counter; C-M2 (C is a maximum count value, M2 is a natural number,
However, it is preset to M2>M1) and is an M binary counter, and only while the carry output from the NG counter is stopped, the number of word clocks is counted and the count value reaches the maximum count value C. a second judgment counter that outputs a carry output, causes the NG counter to set a preset value smaller than the preset value by the carry output, and stops the carry output when the carry output is supplied from the NG counter; (D is the maximum count value, L is a natural number, where M1>L), it is an L-base counter, and counts the number of word clocks only while the carry output from the NG counter is stopped. and outputs a carry when the count value reaches the maximum count value D, and stops the carry output when the carry output is supplied from the NG counter; A NAND output of the carry output and the carry output of the second judgment counter is output as a final judgment result as to whether the data is correct or incorrect, and the carry output of the first judgment counter and the initialization setting pulse generation counter are output. A data judgment circuit characterized in that it outputs an exclusive OR output with a carry output as an initialization setting pulse.