JPH0550171B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a data processing device, particularly to a data processing device that processes data obtained by sampling a temporally continuous analog signal such as an audio signal or a video signal, after passing it through a transmission system such as a recording/reproducing system. It relates to a processing device.

<Description of Prior Art> In data transmitted through a transmission system, data with low reliability may occur due to data errors or lack of data due to, for example, dropouts that occur during recording and reproduction. When such low reliability data (error data) is detected, it is common to replace the detected error data with newly generated data. For example, when error data occurs in a sample data string obtained by sampling an audio signal, a method has been used in which the error data is replaced with interpolated data obtained using data before and after the error data. The methods include the pre-hold method, in which the data immediately before the error data is used as interpolation data, the average value interpolation method, in which the average value of the data immediately before and after the error data is used as the interpolation data, and the A cubic interpolation method using interpolated data obtained from (at least four) data is known.

In terms of the degree of approximation of such interpolated data to the original signal data, the previous value hold method is the worst, followed by the average value interpolation method and the cubic interpolation method, which are better in that order, but the scale of the hardware also increases accordingly. I get used to it. In particular, in the cubic interpolation method, there must be at least two pieces of highly reliable data (non-error data) before and after the error data, and four pieces of data that are separated by a large time interval must be present. Since the interpolated data is obtained by calculation using a large-scale calculation circuit, the hardware configuration becomes extremely complicated. Therefore, it is not used particularly in consumer equipment, etc., except when interpolating with very high precision.

On the other hand, the prior value hold method has the advantage of an extremely simple configuration, but as shown in FIG. 1, the interpolated data is not very close to the analog original signal. In FIG. 1, the dotted line is the analog original signal, ◯ indicates non-error data, × indicates ideal interpolated data, and △ indicates actual interpolated data.

In addition, the average value interpolation method can be implemented using a simple circuit configuration as described below.
Even with this, as shown in FIG. 2, the approximation of the interpolated data to the analog original signal is not sufficient. Note that the dotted lines, ○, x, and △ in FIG. 2 are the same as those in FIG. 1, respectively.

<Object of the Invention> The present invention has been made in view of the above-mentioned drawbacks, and provides a data processing device that has a simple hardware configuration and is capable of replacing error data with highly accurate interpolation data. The purpose is to provide

<Explanation based on Examples> The present invention will be described in detail below using Examples.

FIG. 3 is a diagram showing a data processing device as an embodiment of the present invention. In Figure 3, DATA−
IN indicates input data, and DATA-OUT indicates output data. 2 is the timing clock input terminal,
4 is an input terminal for a well-known error detection signal synchronized with a timing clock. As is well known, the error detection signal is obtained by checking the parity word and CRCC, and when DATA-IN is error data, it is "1", and when it is non-error data, it is "0" from terminal 4. shall be entered.

6, 8, and 10 are data latch circuits that are each operated by a clock pulse and output the input data with a delay of one sampling period; 12 and 14 are full adder circuits; and 16 and 18 are each one of the two input data. data selector to select and output,
20, 22, 24 are subtraction circuits, 26 is a doubling circuit that doubles the data value and outputs it, 28, 3
0, 32, and 34 are inverters, 36 is a latch circuit that delays the error detection signal by one sampling period, and 38 is an exclusive OR circuit (EXOR).

In this example, DATA-IN and DATA-OUT each handle binary data using 2'S complement. In FIG. 3, the full adder circuit 12,
14 outputs data (including carry) that is 1 bit more than the two input data, and serves as a component of an average value calculation circuit. In other words, when obtaining the average value of two data A and B, each data A and B are
Binarized data is generated using offset binary from 2'S complement. Then, by adding all of these bits, removing the least significant bit (LSB), and shifting the other high-order bits by 1 bit, average value data can be obtained as binarized data using offset binary. Conversion between offset binary and 2'S complement is performed by inverting the most significant bit (MSB) of each data. This is done by inverters 28, 30, 32 and 34, respectively.

FIG. 4 is a timing chart showing the waveforms of each part of FIG. 3 a to e, and the operation of each part of FIG. 3 will be specifically explained below using FIG. 4. Figure 4 e
In the figure, ◯ indicates non-error data, × indicates interpolated data by the average value interpolation method, △ indicates interpolated data according to the configuration shown in FIG. 3, and dotted lines indicate original analog signals.

First, the operation when obtaining interpolated data _F4 between the non-error data shown at _D3 and the non-error data shown at _D5 in the figure will be explained. The data output from the latch circuit 6 is error data, and correspondingly, the output of the latch circuit 36 becomes "1". The output of the latch circuit 36 from the selector 18 is “1”
When , among the output data of the full adder circuit 14
The MSB is inverted and the LSB removed is output,
When it is "0", the output data of the latch circuit 6 is output. Therefore, in this case, the former will be output.

The full adder circuit 12 outputs the average value data (offset binary) of the data _D5 inputted as DATA-IN at this time and the data _D3 outputted by the latch circuit 8. On the other hand, D ₃ or D ₅ is output from the selector 16, converted into offset binary data, and then supplied to the full adder circuit 14 together with the average value data of D ₃ and D ₅ . Therefore, the data supplied to the H side terminal of the selector 18 is 3D ₃ + when the selector 16 outputs _D3 .
D ₅ )/4, and when outputting D ₅ it becomes (D ₃ +3D ₅ )/4. In other words, the full adder circuit 14 mixes data immediately before and after certain data (in this case error data) at a ratio of 1:3, and
It is possible to output data mixed at a ratio of 3:1, and the selector 16 outputs one of these two data.

Next, the data selection operation by the selector 16 will be explained. Data D ₃ from latch circuit 10
The subtracter ₂₀ obtains (D ₂ -D ₃ ), and the subtracter 22 obtains (D ₃ -D ₅ ). In addition, along with this, 2
The multiplier circuit 26 outputs 2(D ₂ −D ₃ ), and the subtraction circuit 24 outputs {2(D ₂ −D ₃ )−(D ₃ −D ₅ )}. The output of the subtraction circuit 24 shows a second-order differential characteristic between data D ₂ to data D ₅ of the analog original signal, and when the output data of the subtraction circuit 24 is positive, it is convex downward, and when it is negative, it is convex. This means that it is convex upward. Also, this is indicated by the MSB (shown in Figure 4b) of the output data of the subtraction circuit 24 since the data is based on 2'S complement; when this is "1" it is convex upward, and when it is "0" Sometimes it becomes convex downward. On the other hand, the MSB (4th
(shown in Figure c) becomes "0" when data _D3 is larger than data _D5 , and becomes "1" when it is smaller.

Now, there are generally three pieces of temporally continuous data A,
Assume that there are B and C, and B is error data.
At this time, the value of the analog original signal at sampling timing B, that is, the ideal interpolated data F, is the average value of A and C (A+
When it is smaller than C)/2 and convex upward, it is (A+C)/
Greater than 2.

In the example of finding F ₄ in Figure 4, based on this idea, the analog original signal is convex upward (the subtraction circuit 24
When the MSB of the output data is “1”), D ₃ and
The selector 16 outputs the larger data among _D5 . In other words, the output data of the subtraction circuit 22
When the MSB is "0", _D3 is output, and when it is "1", _D5 is output. Also, the MSB of the output data of the subtraction circuit 24
is “0”, the output data of the subtraction circuit 22
When the MSB is "0", _D5 is output, and when it is "1", _D3 is output.

Therefore, the MSB of the output data of the subtraction circuit 24,
It is sufficient to output D ₃ when the exclusive OR of the MSB of the output data of the subtraction circuit 22 is "1", and output D ₅ when it is "0". In the case of the analog original signal shown in FIG. 4e, the output data of the subtraction circuit 24 is positive, so its MSB is "0", and the output data of the subtraction circuit 22 is negative, so its MSB is "1". The output of EXOR 38 is "1", and selector 16 outputs _D3 . For this reason, selector 1
The output of 8 is (3D ₃ +D ₅ )/4. It will be clear from FIG. 4e that this value is approximated to the original analog signal as interpolated data.

Similarly, one of the two calculation data is selected for F ₈ , F ₁₁ , and F ₁₅ in FIG. 4e,
F ₈ = (D ₇ + 3D ₉ )/4, F ₁₁ = (3D ₁₀ + D ₁₂ )/4,
We get F ₁₅ = (D ₁₄ +3D ₁₆ )/4.

According to the data processing device configured as described above, two calculation data are obtained from the data before and after the error data, and one of them is used to perform interpolation.
With a relatively simple hardware configuration, we were able to obtain interpolation data that was much closer to the analog original signal than average value interpolation.

FIG. 5 shows a data processing device as another embodiment of the present invention. The example shown in FIG. 5 is particularly effective when the analog original signal has a waveform centered around the 0 level, and further simplifies the hardware. In FIG. 5, the same components as in FIG. 3 are given the same numbers, and detailed explanations are omitted.

An analog signal centered around the 0 level generally has an upward convex above the 0 level, and a downward convex below the 0 level. Therefore, instead of the MSB of the output data of the subtraction circuit 24 shown in FIG. 3, the MSB of the output data of the full addition circuit 12 is used.

A case in which the interpolated data _F4 in the timing chart of FIG. 4 is obtained will be specifically described below.
The output data of the full adder circuit 12 is (D ₃ +D ₅ )/2
Therefore, it is possible to determine with a fairly high probability whether the analog original signal is positive or negative at the timing when interpolated data is obtained. This shows the second-order differential characteristics of the analog original signal centered around the 0 level. That is, when the output data of the full adder circuit 12 is positive, the analog original signal is convex upward, and when it is negative, it is convex downward. However, the output data of the full adder circuit 12 is based on offset binary;
When the MSB is "1", it is convex upward, and when it is "0", it is convex downward. This corresponds to the MSB of the output data of the subtraction circuit 24 shown in FIG. 3 above, only for the analog original signal centered around the 0 level. Therefore, a similar effect can be expected by controlling the selector 16 using the exclusive OR of the MSB of the output data of the full addition circuit 12 and the output data of the subtraction circuit 22.

According to the data processing circuit having the configuration shown in FIG. 5, interpolated data with high approximation accuracy can be obtained with an extremely simple hardware configuration.

The embodiments shown in FIGS. 3 and 5 have been explained only in the case where two types of calculation data are selected, but if the number of types is increased, the hardware configuration becomes slightly complicated, but it is possible to achieve even more accurate approximation. It becomes possible to obtain interpolated data.

FIG. 6 is a diagram showing an embodiment in which three types of calculation data are selected. Components in FIG. 6 that are similar to those in FIG. 5 are given the same numbers. Note that this example is also effective for data obtained by sampling an analog original signal with the 0 level as the center level.
In this example, in addition to selecting the calculation data using the above-mentioned quadratic differential feature, in areas where the analog original signal has almost no unevenness, the average value of the data immediately before and after the low reliability data is interpolated. It is intended to be used as data.

In Figure 6, it is noted that the part with almost no unevenness is near the 0 level, and the average value data of the data immediately before and after the low reliability data is 0.
If it is near the level, the average value data is used as interpolation data. 40 is an inverter for converting data based on offset binary into data based on 2'S complement; 42 is predetermined comparison data (X);
43 is a subtraction circuit, 44 is an addition circuit, 45 is a NOR circuit, and 46 is a data selector.

The operation will be explained below. The EXOR 38 outputs "1" or "0" according to the above-mentioned second-order differential characteristics, and the full adder circuit 14
outputs data that is a 1:3 or 3:1 mix of the data immediately before and the data immediately following the error data (based on offset binary), and becomes one of the two inputs of the selector 46. On the other hand, the output data of the full adder circuit 12 excluding the LSB is their average value data, and this average value data becomes the other of the two inputs of the selector 46. Now, when the value of this average value data is y, the condition that the absolute value of y is smaller than x, that is, y is around 0 level is -x
<y<x. In other words, x-y>0 and y+
It is sufficient if x>0, and the subtraction circuit 43 and addition circuit 44 are hardware configurations of this. In other words, the output data of the subtraction circuit 43 and the addition circuit 44 are both positive, that is, their output data
When both MSBs are "0", it can be determined that the analog original signal has little unevenness. At this time Noah Gate 45
outputs "1", and the selector 46 outputs the above-mentioned average value data.

According to the configuration described above, three types of calculation data obtained by mixing the data immediately before and the data immediately after the error data at a ratio of 3:1, 1:1, and 1:3 are selectively used as interpolation data as the error data. By performing this substitution, the accuracy of approximation to the original analog signal can be greatly improved with a relatively simple hardware configuration.

Of course, when the output of the subtraction circuit 24 of the device shown in FIG. 3 is near 0, the average value data can be used, and the configuration can be applied to data obtained by sampling any analog original signal. .

In addition, in the apparatus of each of the above-mentioned embodiments, the data immediately before and after the error data are mixed at a ratio of 3:1 or 1:3, as is clear from each embodiment. This is because it can be easily configured by a combination of two average value calculation circuits, and the average value calculation circuit has an extremely simple hardware configuration. In other words, the hardware configuration for obtaining a plurality of calculation data can be easily configured by using a plurality of average value calculation circuits.

<Effects of the Invention> As explained above, according to the present invention, the values of the first data immediately before the error data and the second data immediately after the error data are compared, and the analog signal waveform near the error data is determined to be higher. It is determined whether the analog signal waveform is upwardly convex or downwardly convex, and using the comparison result and the discrimination result, if the analog signal waveform is upwardly convex, the value of the first data and the second data is determined. Large data is weighted more than data with small values, and when the analog signal waveform is convex downward, data with small values of the first data and second data is weighted more than data with large values. By performing weighting and replacing the error data with data obtained by adding the weighted first data and the second data, an extremely analog original signal can be obtained with a simple hardware configuration. It is possible to obtain data that approximates .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing how data is replaced in the conventional pre-hold method, FIG. 2 is a diagram showing how data is replaced in the conventional average value interpolation method, and FIG. 3 is a diagram showing how data is replaced in the conventional mean value interpolation method. FIG. 4 is a timing chart showing waveforms of each part of FIG. 3, FIG. 5 is a diagram showing a data processing device as another embodiment of the present invention, and FIG. FIG. 7 is a diagram showing a data processing device as another example. Numerals 6, 8, and 10 are latch circuits, 12 and 14 are full adder circuits included in the arithmetic means, 16 is a data selector included in the selection means, and 18 is a data selector included in the replacement means.

Claims (1)

[Claims] 1. A device for processing a sample data sequence obtained by sampling a temporally continuous analog signal, which compares the values of first data immediately before error data and second data immediately after error data. a comparing means for determining whether the analog signal waveform in the vicinity of the error data is convex upward or convex downward; When the waveform is upwardly convex, the data with a larger value of the first data and the second data is weighted more than the data with a smaller value, and when the analog signal waveform is downwardly convex, Arithmetic means for weighting data with a smaller value greater than data with a larger value among the first data and the second data, and adding the weighted first data and the second data. and replacement means for replacing the error data with the data obtained by the calculation means.