JPH0227676B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device, and particularly to a raster scan type CRT display device.

In a CRT display device, information to be displayed is written into a refresh memory, and information read from the refresh memory is displayed on the display screen.

Coded characters in reflex memory,
When writing symbol information, the code information from the refresh memory is converted into a pattern signal in the form of dots by a pattern generation circuit, and then displayed on the display screen. In this case, since the characters and signal information are encoded and stored, a relatively large amount of display information can be written into the refresh memory. On the other hand, it is not possible to store or display arbitrary patterns that are not coded.

On the other hand, when dot information is written in the refresh memory, the dot information is displayed on the display screen, so that any pattern can be displayed. On the other hand, since information (dot information) in one-to-one correspondence with each display dot on the display screen is written into the refresh memory, information for a wide display area cannot be written.

Japanese Patent Laid-Open No. 52-2223 discloses a method for displaying character patterns and graph patterns using a memory device (refresh memory) that stores character codes or graph patterns and classification bits for each memory word consisting of 8 bits. A possible graph display method is described. However, in this conventional method, a distinguishing bit is provided for each word in memory, so
There are restrictions on increasing the number of character codes and increasing the storage capacity of graph patterns. In addition, in this method, when writing information to a storage device, a distinguishing bit is added to each character code or graph pattern sent from an electronic computer or the like, so the configuration becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device that can expand the functions of the display device, can be miniaturized, and can be implemented at low cost.

According to the present invention, a flip-flop circuit is provided to which a display mode control signal is applied from the microprocessor via a bus line, and when the display mode control signal indicates code information, the flip-flop circuit reads out code information from the refresh memory. The code information read out from the refresh memory is converted into dot information by the pattern generation circuit and displayed on the display screen, and when the display mode control signal indicates dot information, the information read from the refresh memory is That is, the dot information is displayed as is on the display screen.

According to the present invention, two display modes, code information display and dot information display, are instructed by using the flip-flop circuit as described above, and the refresh memory is used effectively for display. It will be possible to use it. Furthermore, since the flip-flop is controlled by using the functions of a microprocessor, operation control can be easily performed, and such operation control can be performed without significantly increasing the circuit scale. .

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The outline of the CRT display device in this embodiment is as follows.

Information to be displayed is written into the refresh memory 5 by an input source (not shown) such as a keyboard or a CPU (microprocessor). In this case, either coded character/symbol information or dot information for forming an arbitrary figure is written into the refresh memory 5. Therefore, the refresh memory 5 has a memory capacity for at least one screen displayed on the CRT. The information written in the refresh memory 5 is read out for each character, symbol code information, or multiple dot information in synchronization with the raster timing of the CRT. The above code information is converted by a pattern generation circuit (pixel memories: 8, 9) into a pattern signal having a dot configuration for each character and symbol. The pattern generation circuits 8 and 9 generate characters referenced by code information,
It stores symbol patterns and is generally constructed from read-only memory ROM. Therefore, code information such as characters to be displayed is transferred from the refresh memory 5 to the pattern generation circuit 8,
By specifying the addresses of the pattern generation circuits 8 and 9, the pattern generation circuits 8 and 9 output pixel data such as characters in synchronization with the raster scan timing. On the other hand, since the contents of the refresh memory 5 constitute pixel data, arbitrary graphic information is directly used as pixel data by reading it out.

These pixel data are converted into serial data by parallel/serial conversion circuits 10 and 11, respectively, and converted into video signals for each raster. This video signal is combined with a synchronizing pulse by the video control circuit 13 and supplied to the CRT device to draw characters, symbol patterns, or arbitrary graphic patterns on the CRT tube surface.

The timing controller 4 forms address timing pulses for the refresh memory 5, clock pulses CLK which are the basis of raster address timing pulses for the pattern generation circuits 8 and 9, timing pulses for serially converting pixel data such as character patterns, etc. It is something.

The CRT control circuit 1 includes a horizontal display character register (in the case of dot display, it becomes a dot number register), a vertical display character register (in the case of dot display, it becomes a vertical dot number register), etc., although the details are not shown in the figure. various control registers, characters, symbols, and lines (dot sets and lines in the case of dot display) counters for specifying addresses in the refresh memory 5, in other words, specifying addresses on the CRT screen;
It consists of a CRT horizontal and vertical synchronization signal generation circuit, a raster control circuit, a cursor control circuit, etc. This allows the address specification of the refresh memory 5 and the raster specification of the pattern generation circuits 8 and 9 to be synchronized with the raster of the CRT, thereby forming the above-mentioned pixel data and synchronization pulses for CRT display. be.

This CRT control circuit is, for example,
HD46505" monolithic semiconductor integrated circuit can be used.

The clocks formed in the device of this embodiment include a basic clock (character clock: CLK) for sending to the CRT control circuit 1, a video clock VCLK related to the video signal,
That is, it can be broadly classified into a shift clock of a shift register (parallel/serial conversion circuit) used to convert pixel data into a serial signal.
The following close relationship is given between these two, CLK and VCLK. That is, the character clock CLK is a timing pulse that defines the display period of one character in the horizontal direction, and the video clock VCLK is a timing pulse that defines the number of dots in the horizontal direction in one period (one display timing) of the character clock. It is said that

Now, for example, as shown in Figure 2,
The display screen 24 is configured by setting the number of rasters constituting the display screen section 23 of the CRT 22 to 240, setting the horizontal scanning time to 54.16 μs, and providing blanking sections of 10% each on the top, bottom, left and right sides of the display screen section 23. It shall be. Then, on the display screen 24, 1
As shown in FIG. 3, if the character display screen 25 is composed of horizontal dots and 12 vertical rasters (dots), and it is provided with 64 characters/line and 16 lines, one cycle of the video clock VCLK ( t _VCLK ) is calculated using the following equation (1).

t _VCLK = 54.16×0.8/7×64 = 0.096714 (μs) On the other hand, one period (t _CLK ) of the character clock CLK is obtained by the following equation (2).

t _CLK = 54.16 x 0.8/64 = 0.677000 (μs) The display screen section 23 configures a raster in non-interlace mode, and has 240 lines, which is 91.4% of the 262.5 lines on a general home television receiver.
Using books, other rasters are assigned to the blanking period. Also, the scanning time is 9.3 with blanking time
(μs), and the total horizontal scanning time is 63.5 (μs).

Therefore, to obtain a screen with the above character structure, a frequency signal of 10.339764MHz is required.
In FIG. 1, an oscillation circuit 2 is for forming this frequency signal. However, it is not possible to display characters using the above-mentioned frequency signals on home television receivers due to bandwidth constraints. For this reason, when using a home television receiver, the dot frequency (video signal frequency) is reduced to 1/2 by using a horizontal 32 character configuration.

In addition, when the entire screen is made up of dots in order to draw an arbitrary figure, the display screen 25' is made up of 128 dots horizontally and 96 bits vertically, and the video clock is calculated using the same calculation as above, as shown in FIG. When calculating VCLK, t _VCLK = 42.3/128 = 330.468 (ns). If this clock is divided into 1/3 and used, the required frequency will be 9.0780141MHz,
In FIG. 1, an oscillation circuit 3 forms this.

Note that the horizontal to vertical ratio of the display screen 24 in FIG. 2 or 4 is both set to 4:3, and the number of rasters on the display screen 24 is 240×0.8=
The number is set at 192. Therefore, the unit dots 28 in FIG. 4 are 128 dots in the horizontal direction and 96 dots in the vertical direction, forming the above-mentioned 4:3 display screen, so the unit shape is a square. With such unit dots, when drawing an arbitrary figure, the bit pattern in the reflash memory 5 corresponds to the display pattern, which simplifies the program for forming the figure pattern.

In case of character pattern display, horizontal 7 x 64 (or
32) Dots, 192 dots vertically. Therefore,
In the case of horizontal 32 character display, the shape of the dot is approximately square, and in the case of 64 character display, it is a vertically long rectangle. However, in the case of displaying characters and symbols, accuracy is not required for the pattern shape, so there is no problem.

In the case of displaying characters and symbols, the number of dots shall be determined by considering the bandwidth (resolution) of the CRT, and the number of dots for displaying arbitrary figures shall comply with the above square condition and resolution. When determining the number of dots,
In order to be able to determine the dot frequency that satisfies each condition, it is advantageous to provide two oscillation circuits as shown in this embodiment in order to simplify the CRT display system.

In other words, if you try to configure it with one oscillation circuit, the video clock VCLK that satisfies the above conditions will be
The circuit configuration of the timing controller 4 that forms the circuits, etc. becomes extremely complicated, and the original oscillation frequency must be extremely high, which is impractical.

In this embodiment, the refresh memory 5 shown in FIG.
It has a storage capacity of bytes, and the storage address is a decimal number.
0000 to 2047. In a microcomputer system, the refresh memory 5 is assumed to have storage addresses B000 to B7FF in hexadecimal notation, for example. The address information for the refresh memory 5 by the CRT control circuit 1 is information in an 11-bit configuration MA ₀ to MA ₁₀ . Address information MA ₀ to MA ₁₀ from the CRT control circuit 1 is input to the refresh memory 5 via the address selector 6. This address selector 6 has an output from an address decoder 7 that converts address information (B000 to B7FF) supplied from an input source such as a CPU via an address bus ADDRESS into the 11-bit refresh memory address information, and the above
This is for switching between address information and the CRT control circuit.

The storage capacity of this refresh memory 5 is 2048 bytes as described above. Accordingly, when displaying characters of 32 characters x 16 lines, the refresh memory 5 has a capacity of 4 pages, since one page is 512 bytes, and when displaying characters of 64 characters x 16 lines. Since one page is 1024 bytes, it has the capacity of two pages. Since 128 x 96 dot display requires 128 x 96/8 = 1536 (bytes), the above storage capacity (2048 bytes) will hold the dot information that makes up one screen. can do. In this embodiment, as mentioned above, one refresh memory 5 is used for displaying characters and symbol patterns as well as for displaying dots, so the CRT display system can be simplified while expanding the display functions. It is possible to aim for

Generally, the character code uses ASCII code, and 64 characters are expressed with 7 dots.

In this embodiment, the refresh memory 5
It has a 1-byte configuration, that is, an 8-bit configuration, and paying attention to the fact that the most significant digit of the 8-dot information is "0" in the above ASCII code, in the case of symbols other than the above characters, The most significant digit above is "1". This forms arbitrary code information.

The pattern generation circuit 8 converts the character code (ASCII code) into pixel data, and the pattern generation circuit 9 converts the arbitrary symbol code into pixel data. Switching between the two is performed by "0" and "1" of the most significant digit, and the output of either pattern generation circuit 8 or 9 corresponding to the most significant digit is selectively output, and parallel/serial conversion is performed. The signal is sent to circuit 10.

In this case, the pattern generation circuits 8 and 9 are required to output 7 x 12 bits of information since one character structure 25 is composed of 7 x 12 dots as shown in Fig. 3. . Here one character composition 25
The character part 2 consists of 5 x 7 dots as shown in the figure.
7, consisting of one row at the top, one column each on the left and right, and four rows at the bottom. Therefore, in order to reduce the storage capacity, the character pattern generation circuit 8 writes pixel data for expressing one character using 7.times.8 dots 26.

The space that forms the space between the lines of characters (the cursor display area) has a raster address of 8 to 11, and expressed in binary information as "1", "0", "0", "0" to
Focusing on the fact that the values are "1", "1", "0", and "0", if the raster information RA ₃ of the most significant digit is "1", the pixel data of the black level (spatial level) is outputted unconditionally. It is intended to do so.

As shown in FIG. 3 and described above, the character display section 27 has one dot space at the top and left and right sides, and a four dot space at the bottom. Therefore, as shown in the figure, there are spaces of 2 dots between characters and 5 dots between lines to make the characters easier to see. especially,
The one dot space on the top, left, and right is
Display screen 2 when displaying text in black and white inverted display
4, the boundary line of the CRT screen 23, and the characters displayed in black form a white space to facilitate the deciphering of the characters.

Here, FIG. 3 is for explaining the operation of the pattern generation circuit 8. Alphabetical character "A" information written in the pattern generation circuit 8 is transferred to the character clock CLK and the video clock.
This shows how dots are displayed on the screen by associating the horizontal time allocation with VCLK and the raster address. When the timing and raster are expressed in a matrix, the ○ marks at the intersections are white. Displayed as a dot (black if inverted).

Then, R ₁ and R ₂ become video signals output from the parallel/serial conversion circuit 10 in each raster R ₁ and R ₂ .

On the other hand, in the case of dot display, the 8-bit information read out from the refresh memory 5 directly becomes pixel data, so as shown in FIG. is directly input to the parallel/serial conversion circuit 11 and converted into a video signal.

The video output of characters and the like and the video output of dot display are switched by the gate circuit 12 and input to the video control circuit.

Consists of one parallel/serial conversion circuit,
A switching gate circuit may be provided on the input side, but in this case, the gate circuit becomes complicated because there are eight pieces of information to be switched. The parallel/serial conversion circuits 10 and 11 can be configured with shift registers and have a simple circuit;
Since switching of the shift clock (video clock VCLK) becomes unnecessary, it is better to provide two parallel/serial conversion circuits as shown in this embodiment.

Here, the timing controller 4 and the gate circuit that switches between the parallel/serial conversion circuits 10 and 11 are controlled in a corresponding manner. That is, as shown in FIGS. 2 and 4, the so-called pattern display of characters and the dot display have different dot configurations (screen configurations), so the character clock CLK and video clock VCLK are adjusted accordingly. This is because it is necessary to form a video signal based on this.

Therefore, as shown in FIG. 5, the timing controller 4 includes the oscillation circuits 2 and 3 described above.
A switch circuit SW ₁ that switches the output of , switch SW ₃ for switching between the above 32 characters/line and 64 characters/line, switch circuit SW ₂ for switching between the above pattern display and dot pulse for dot display, and a 7/8-decimal switching counter circuit that forms the character clock CLK. 31. The video (dot) clock VCLK sent to the parallel/serial conversion circuits 10 and 11 corresponds to the signal on the input side of the switch circuit SW ₂ , so the corresponding parallel/serial conversion circuits 10 and
11.

In case of pattern display, one character is 7 horizontally.
Since it is composed of dots, it can be calculated using a hexadecimal counter.
A character clock CLK is formed, and in the case of dot display, it is composed of eight dots in a timing period corresponding to one character, so it must be formed by an octal counter. The gate circuit _G1 is a control circuit for a heptadary/octal counter, and operates as a heptadary counter when the control signal MODE is "1", and its operation diagram is shown in FIG. This control signal MODE is a display mode control signal for switching between so-called pattern display and dot display, and is used to control the switch circuits SW ₁ and SW ₂ and the gate circuit 12. . This control signal MODE is formed by the flip-flop circuit 15 shown in FIG.
Alternatively, by writing "1", the switches and gates necessary for switching the series of display modes described above are changed.

Note that FIG. 6 shows an operation waveform diagram for only the heptadary counter operation, and the octal counter operation is well known and will therefore be omitted. The output of the gate circuit _G1 in this counter circuit is used as a set pulse to input pixel data from the pattern generation circuits 8 and 9 of the parallel/serial conversion circuit 10 at the rising timing, and the gate circuit _G2 is used at the rising timing. It is used as a set pulse for inputting pixel data from the refresh memory 5 of the parallel/serial conversion circuit 11.

Thereby, for example, as shown in FIG. 3, pixel data can be converted into continuous video signals R ₁ and R ₂ .

In FIG. 1, video control circuit 1
3 is for forming a composite video signal, and is connected to the parallel/serial conversion circuit 10 or 1.
The video signal formed by 1 and the synchronization pulse etc. (H/V SYNC,
DISPTMG).

As this specific circuit, for example, the one shown in FIG. 7 can be used. This circuit is
a voltage divider circuit including resistors R ₁ to _{R 3} that form three levels of a black level, a white level, and a synchronization pulse level;
Inverter circuits IN ₁ each having an open collector configuration are provided at the connection points of the above-mentioned resistors R ₁ to R ₃ ,
It is composed of IN ₂ and emitter follower circuits Q ₁ and R ₄ that constitute the output circuit.

A video signal in which the video signal formed by the parallel/serial conversion circuit 10 or 11 and the horizontal and vertical blanking signals DISPTMG formed by the CRT control circuit 1 are combined is input to the inverter circuit IN ₂ . , horizontal and vertical synchronizing pulses (H/V SYNC) generated by the CRT control circuit ₁ are input to the inverter circuit IN1.

When the above video signal is “1”, the output of inverter circuit IN ₂ is “0”, that is, the resistance
Short-circuit _R3 to form a black level signal determined by the ratio of resistors _R1 and _R2 , and when it is "0", the resistor _R1 and
A white level determined by the ratio of R ₂ and R ₃ is formed.

On the other hand, the synchronization pulse (H/V SYNC) is “1”
At this time, the output of the inverter circuit IN ₁ is "0", that is, the resistors R ₂ and R ₃ are short-circuited to lower the voltage to the 0V level, thereby forming a synchronizing pulse level. As a result, a composite video signal as shown in FIG. 8 can be obtained.

The blanking signal DISPTMG forming the video signal is for setting the CRT screen outside the display screen 24 in FIG.
The vertical direction is formed based on the output of the row counter.

In this embodiment, an inversion control circuit (not shown) is provided on the output side of the parallel/serial conversion circuits 10 and 11 via the gate circuit 12.
It provides a function to invert the black and white of the display screen. This inversion gate circuit uses, for example, an exclusive OR circuit, and uses one input as a control input.
By changing it to "0" or "1", it is possible to selectively obtain an output in phase or in phase with the video signal applied to the other input.

This control signal NEG is, as shown in Figure 1,
It is formed by a flip-flop circuit 16. By assigning the address SEOA4, for example, to this flip-flop circuit 16, black and white inversion can be controlled by writing a program of "0" or "1".

Since the video control circuit 13 outputs a composite video signal, it can directly drive a monitor CRT, but when using a home television receiver as a CRT, VHF
(Very High Frequency) wave. The modulation circuit 14 is for this purpose, and forms a modulated signal using, for example, one channel (91.25 MHz) or two channels (97.25 MHz) in the standard television band, and inputs it from an antenna terminal.

In this example, as shown in FIG.
A state detection circuit 19 is provided to detect the CRT display period. For example, address SEOA8 is given to this state detection circuit 19 to determine whether or not the refresh memory 5 can be accessed from the CPU. That is, when the CPU accesses the reflash memory 5, it specifies the detection circuit 19 and learns the state of the control signal SEL of the address selector 6 to perform writing or the like. At this time, it is desirable for the write program to perform state detection again after executing the write command, and confirm whether or not writing has actually been performed by checking whether or not it is in a writable state.

Also, data bus DATA, address bus
Set up RAM20 and ROM21 in ADDRESS,
We are trying to expand the memory of the CPU.
These memories 20 and 21 serve not only as a mere extension of the CPU's memory as described above, but also as a CRT display device, the refresh memory 5 is used in common for pattern display and dot display, as described above. Therefore, when both are displayed alternately, the information can be protected by using it for saving the refresh memory 5.

In this way, the refresh memory 5 and the other memories 20 and 21 are provided on the same bus, and
Exchange of information between the CPU and memories 20 and 21,
The bus driver 17 is especially provided to prevent information interference when reading out the refresh memory 5 at the same time during CRT display operation.

The bus driver 18 is an input source for the CPU and a CRT.
This is necessary between the display device and the display device.

The present invention is not limited to the above-mentioned embodiments, and any specific configuration may be used as long as the refresh memory 5 is a CRT display device that can be used for both pattern display and dot display. It's okay to have it. Further, the number of dots constituting characters etc. can be varied in various ways, and it goes without saying that the pattern generation circuit 9 is unnecessary when no special symbol is displayed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention, FIGS. 2 and 4 are diagrams showing the screen configuration of a CRT showing an embodiment of the invention, and FIG. 3 is a block diagram showing an embodiment of the invention. FIG. 5 is a diagram explaining the operation of a pattern generation circuit showing an embodiment, and FIG. 6 is a specific circuit diagram of a timing controller showing an embodiment of the present invention.
7 is a specific circuit diagram of a video control circuit showing an embodiment of the present invention, and FIG. 8 is a diagram of its operating waveforms. 1...CRT control circuit, 2, 3...oscillation circuit,
4... Timing controller, 5... Refresh memory, 6... Address selector, 7... Address decoder, 8, 9... Pattern generation circuit,
10, 11...parallel/serial conversion circuit, 1
2... Gate circuit, 13... Video control circuit, 14... Modulation circuit, 15, 16... Flip-flop circuit, 17, 18... Bus driver, 19... Status detection circuit, 20... RAM, 2
1...ROM, 22...CRT, 23...display screen section, 24...display screen, 25...1 character display screen, 27...character display section, 28...dot, 2
9, 30... Frequency dividing circuit, 31... Counter circuit.

Claims (1)

[Scope of Claims] 1. Storage means 5 for storing information to be displayed on a display screen, pattern generation means 8 and 9 for converting code information into dot information, and a microprocessor via bus lines DATA and ADDRESS. display control means adapted to be coupled to and sequentially form address information for said storage means 5 in synchronization with said synchronization signal together with a synchronization signal for display; and a display control means directed by a microprocessor. When an address is given, a display mode control signal indicating whether the multiple bits of information read out in parallel from the storage means 5 is in the form of code information or dot information is sent to the microprocessor via the bus lines DATA and ADDRESS. The operation of the flip-flop circuit 15 is controlled by the display mode control signal from the flip-flop circuit 15, and when the display mode control signal indicates dot information, the information is read from the storage means 5. is displayed as is on the display screen, and when the display mode control signal indicates code information, the information read from the storage means 5 is converted into dot information by the pattern generation means and then displayed on the display screen. 1. A display device comprising: switching means 12 for switching and displaying information from the storage means and information from the pattern generation means so as to display the information.