JPS61193196A - CRT display method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT display system using a rask scan method.

Note that a display device using the Rusk scan method is disclosed in, for example, Japanese Patent Laid-Open No. 147026/1983.

In addition to using the refresher memory in a CRT display device to store coded character and symbol information, the present invention also provides a CRT display device in which the refresher memory can be used to store dot information for drawing arbitrary figures, etc. configuring a system, or switching between display using coded characters and symbols and direct display using dots after converting them into video signals independently of each other; By providing dedicated oscillation circuits for each, it is intended to expand the functions of the CRT display device while simplifying the system configuration.

Another object of the present invention is to provide a new CRT display method.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The outline of the CRT display device in this example is as follows:
It is as follows.

Information to be displayed on the refresh memo January 51 is written by an input source (not shown) such as a keyboard or CPV (microprocessor). In this case, the refresh memory (5)K stores coded character and symbol information,
Any of the dot information for configuring an arbitrary figure is written. Therefore, the refresh memory (5) has a memory capacity for at least one screen displayed on the CRT. The information written above is one character, synchronized with the raster timing of the CRT.
It is read out for each symbol code information or multiple dot information. The above code information is the pattern generation circuit (pixel memo +
J: 8, 9), each character and symbol is converted into a pattern signal composed of dots.

The pattern generation circuits (8, 9) store character and symbol patterns, and are generally constituted by a read-only memory (ROM). Therefore, by providing the pattern generation circuit (8, 9) K from the flexible memory (5) for the characters to be displayed, that is, by specifying the address of the pattern generation circuit (8, 9), its output is Outputs pixel data such as characters in synchronization with raster scan timing. On the other hand, since the contents of Refrange Memo January 5) constitute pixel data, the arbitrary graphic information is read out and used directly as pixel data.

These pixel data are processed by a parallel/7 real conversion circuit (
10 and 11), the signals are converted into serial data, and converted into video signals for each raster. This video signal is combined with a synchronizing pulse by a video control circuit (13) to draw characters, symbol patterns, or arbitrary graphic patterns on the CRT tube surface.

The timing controller (4) serially converts pixel data such as the address timing pulse of these refresh memos (January 5), the tarokk pulse (CLK) which is the basis of the last address timing pulse of the pattern generation circuit (8, 9), and character patterns. It forms timing pulses and the like for conversion.

The CRT control circuit il+ includes various control registers such as a horizontal display character register (for dot display, it becomes a dot set register), a vertical display character register (for dot display, it becomes a vertical dot number register), Refresh memory (5), in other words, a character, symbol, and line (dot group and line in the case of dot display) counters for specifying addresses on the CRT screen, a CRT horizontal and vertical synchronizing signal generation circuit, and a raster Control circuit, cursor control circuit, etc.
It consists of From this K, address specification of the refresh memory (5) synchronized with the CRT raster and raster specification of the pattern generation circuit (8, 9) are performed to form pixel data as described above, and synchronization for CRT display. It forms a pulse.

This CRT control circuit is, for example, "product model name HD465".
A 05J monolithic semiconductor integrated circuit can be used.

The clock in this embodiment is the CRT control circuit f
Basic clock sent to l+ (Kirafuta clock: C
LK') and a video clock (VCLK) related to the video signal, that is, a shift clock of a shift register (parallel/serial conversion circuit) used to convert pixel data into a serial signal. Both of these (CLK.

VCLK). This is because the Kirafuta clock (CLK) is a timing pulse that defines the display period of one character in the horizontal direction, and the video clock (VCLK) is a timing pulse that defines the display period of one character in the horizontal direction.
This is because it defines the number of dots in the horizontal direction at the display timing.

Therefore, for example, as shown in FIG.
The number of rasters composing the display screen section (23) of 22) is set to 2.
It is assumed that the display screen (24) is configured with 40 lines, a horizontal scanning time of 54.16 μs, and blanking portions of 10% each on the top, bottom, left and right sides. Then, as shown in Figure 3, one character display screen (25) is placed in the horizontal 7
64 dots, consisting of 12 vertical rasters (dots)
Assuming that 16 text character lines are provided, one cycle (tVCLK) of the above-mentioned video code (VCLK) is determined by the following equation (11).

ty(LH=54.16X0.8/7X64=0.09
4494 (μS) On the other hand, one period (ICLK) of the Kirafuta clock (CLK) is obtained by the following equation (2).

tcLK""54.16 X O, 8/ 64 = 0.
641458 (μS) Note that the above display screen section (23
) composes a raster in non-interlaced mode, and 9 out of 262.5 on a typical home TV receiver.
Using 240 lines, which is 1.4%, the other rasters are allocated to blanking time. The scanning time is 9.3 (μS) for blanking, and the total horizontal scanning time is 63.
5 (μS).

Therefore, in order to obtain a screen with the above character structure, K is 10.
．． A frequency signal of 582682 MHz is required. 1st
In the figure, the oscillation circuit (2) is for forming this frequency signal. However, it is not possible to display characters using the above-mentioned frequency signals with a home television receiver due to bandwidth limitations. Therefore, when using a home television receiver, the dot frequency (video signal frequency) is divided into 1/2 by using a 32-character configuration.

Furthermore, when the entire screen is made up of dots in order to draw an arbitrary figure, if the K and display screen (25') are 128 dots horizontally and 96 bits vertically as shown in Figure 4, the video can be calculated using the same calculation as above. When looking for Chronok (VCLK),
tvcxJK=42.3/128=330.729(
ns). If this clock is divided into 1/3 and used, the required frequency is 9.0708678MH
z, which is formed by the oscillation circuit +31 in FIG.

Note that the horizontal to vertical ratio of the display screen (24) in FIG. 2 or 4 is both set to 4:3, and the number of rasters on the display screen (24) is 240×0.8. =192
It is set in a book.

Therefore, the unit dora) (28) shown in FIG.
The shape of 8) is a square, and when drawing an arbitrary figure, the bit pattern of Refresh Memo January 5) corresponds to the display pattern, which simplifies the program for forming the figure pattern.

On the other hand, in the case of character pattern display.

Take 7 x 64 (or 32) dots horizontally and 192 dots vertically.

Therefore, in the case of a horizontal 32 character display, the shape of the door is approximately square, but in the case of a 64 character display, it is a vertically long rectangle. However, in the case of displaying characters and symbols, accuracy is not required for the pattern shape, so there is no problem.

From the above, in the case of displaying characters and symbols, the number of dots is determined by considering the bandwidth (resolution) of the CRT.On the other hand, for displaying arbitrary figures, the number of dots is determined by
Since the number of dots is determined by considering the above square condition and resolution, in order to be able to determine the dot frequency that satisfies each condition, two oscillation circuits are used as shown in this example. Providing a CRT display system is advantageous in simplifying the CRT display system.

In other words, if an attempt was made to configure it with one oscillation circuit, the circuit configuration of the timing controller (4) that forms the video clock (VCLK), etc. that satisfies the above conditions would become extremely complex, and it would be necessary to use one with an extremely high original oscillation frequency. It becomes necessary and becomes impractical.

In this embodiment, the refresh memory (5) shown in FIG. 1 has 8 bits per byte, has a storage capacity of 2048 bytes, and has storage addresses from oooo to 2047. In a microcomputer system, for example, it is B000 to BUFF.

Therefore, the address information of CRT control circuit +11 is M
A0~MA,. The information has an 11-bit configuration.

Address information (MA0) from this CRT control circuit (1)
~M A Io ) is input to the refresh memory (5) via the address selector (61). This address selector +61 is connected to the address bus (ADDRESS
), the output of the address decoder (7) which converts into the 11-bit refresh memory address information, and the C
This is for switching the address information of the RT control circuit.

The storage capacity of this refresh memory (51 is 2048
Since it has bytes, in a character display of 32 characters x 16 lines, one page is 512 bytes, so 4
It has a capacity for one page, and since one page is 1024 bytes in a character display of 64 characters x 16 lines, it has a capacity for two pages. Since 128x96 dot display requires 128x96/8 = 1536 (bytes), the above storage capacity 1i (2048 bytes) can hold the dot information that makes up one screen. can. In this embodiment, as described above, one glue fresh memo 5) is used for displaying characters, symbol patterns, and dots, so the display function is expanded. 'The system can be simplified.

Generally, the character code uses an ASCII (ASS[I) code to represent 64 7-pit characters.

In this embodiment, the refresh memory (5) is
Since the byte consists of 8 bits, note that the most significant digit information is '0' in the above ASCII code, and symbols other than the above characters can be arbitrarily set with the above most significant digit being ``1''. It forms the code information of.

The pattern generation circuit (8) converts the above character code (ASCII code) into pixel data, and the pattern generation circuit (8) converts the above arbitrary symbol code into pixel data.
9), and switching between the two is done using the most significant digit (D,) above.
This is done by "O" and "1", and either one is selectively output and sent to the parallel/serial conversion circuit [11m].

In this case, the pattern generation circuits (8, 9) require 7 x 12 bits of information since one character (25) consists of 7 x 12 dots as shown in Figure 3. . However, since the character structure (27) is composed of 5×7 dots, the character pattern generation circuit 1
81 is for writing pixel data for expressing one character using 7×8 dots (26) in order to reduce the storage capacity.

The space forming the line spacing between characters (the cursor display area) is represented by a raster address in 8-11. binary information. 1"10""0"O"～"1""1"'"0"
10", and the raster information of the most significant digit (R
When AM) is "1", it outputs pixel data at a black level (spatial level) without any problem.

Further, as shown in FIG. 3, the K character display section (27) has one dot space each on the left and right sides of the upper part, and a four dot space at the lower part.

Therefore, as shown in the figure, there is a space of 2 dots between characters and a space of 5 dots between lines, which makes the characters appear (in particular, 1 dot at the top, left, and right). The space was provided for the green border between the display screen (24) and the CRT screen (23) when the character display is displayed in black and white inversion.
A white space is formed between the characters displayed in black to make the characters easier to decipher.

Here, FIG. 3 is for explaining the operation of the pattern generation circuit (8). The alphabet character rAJ information written in the pattern generation circuit (8) is input to the character clock (CLK') and the video clock (8). This shows how dots are displayed on the screen by associating the horizontal time allocation by (VCLK) with the raster address, and when the timing and raster are expressed in a matrix, the ○ marks at the intersections are White (black if reversed)
Displayed as a dot.

Then, RI-Rt becomes the video signal output from the parallel/serial conversion circuit (10) in each raster (R1, Rt).

10,000, in the case of dot display, refresher memory (5
) The 8-bit information read from the pixel data directly becomes the pixel data, so as shown in FIG. 11) and is converted into a video signal.

The video output of characters and the like and the video output of dot display are switched by the gate circuit (2) and input to the video control circuit.

Although it is also possible to configure one parallel/serial conversion circuit and provide a switching gate circuit on the input side, in this case, the gate circuit becomes complicated because there are as many as eight pieces of information to be switched. The parallel/serial conversion circuits (10, 11) can be configured with shift registers, have a simple circuit, and have a shift clock (video clock V).
CLK), it is better to provide two parallel/serial conversion circuits as shown in this embodiment.

Here, the timing controller (41) and the gate circuit that switches the parallel/serial conversion circuit (10, 11) are controlled in a corresponding manner.In other words, so-called pattern display such as characters and dot display are Figure 2,
As shown in FIG. 4, the dot configurations (screen configurations) are different, so the character clock (CL) is
K), it is necessary to form a video clock (VCLK), and it is necessary to form a video signal based on this.

Therefore, as shown in FIG. 5, the timing controller (41) includes a switch circuit (SW,) for switching the output of the oscillation circuit (2°3) described above, and a driver for displaying the pattern of 32 character lines. ) 1/2 to form a pulse
A frequency dividing circuit (29), a 1/3 frequency dividing circuit (30) that forms a dot pulse in the case of dot display, and switches (SWs) that switch between the 32-character line and 64-character line.
, a switch circuit (SW, ) for switching between the pattern display and dot pulses for dot display, and a 7/8 base switching counter circuit (31) for forming a character clock (CLK). Video (dots) sent to the above parallel/serial conversion circuit (10, 11)
Since the clock (VCLK) corresponds to the signal on the input side of the switch circuit (SW), it is input to the corresponding parallel/serial conversion circuit (10, 11).

In the case of pattern display, one character consists of 7 horizontal dots, so a character clock (CLK) is formed by a heptadary counter, and in the case of dot display, 8 dots are formed in the timing period corresponding to the character. Since the counter is configured as an octal counter, it must be formed by an octal counter. The gate circuit (G- is a 7/8 decimal counter control circuit, which operates as a 7-ary counter when the control signal (MODE) is 1". Its operation diagram is shown in FIG. 6. The control signal (MODE) is a display mode control signal for switching between so-called pattern display and dot display, and is used to control the switch circuit (SR-S Wt) and the gate circuit (12). This control signal (MODE) is formed by the flip-flop circuit (15) shown in FIG. By writing in the program, the switches and gates necessary for switching the series of display modes described above can be changed.

Note that FIG. 6 shows an operation waveform diagram for only the heptadary power counter operation, and the octal power counter operation is well known and will therefore be omitted. Gate circuit (G1) in this counter circuit
) is used as a set pulse to manually input pixel data from the pattern generation circuit (8, 9) of the parallel/serial conversion circuit (1o) at its rising timing, and the gate circuit (G, ) is used at its rising timing to generate a set pulse. Parallel/Serial Conversion Circuit (11) Glue Freshy Memory (
The pixel data from 5) is used as a manual set pulse.

From this K, for example, as shown in FIG. 3, pixel data can be made into continuous video signals (us, ut).

In FIG. 1, the video control circuit (13) is for forming a composite video signal, and combines the video signal formed by the parallel/serial conversion circuit (10 or 11) with the CRT control circuit +1. ) formed by synchronization pulses etc. (H/V symc.

DISPTMG).

As this specific circuit, for example, the one shown in FIG. 7 can be used. This circuit consists of a voltage divider circuit made up of resistors (R, ~R3) that form three levels of black level, white level, and synchronization pulse level, and a voltage divider circuit made up of resistors (R+~R3) that form three levels: black level, white level, and synchronization pulse level.
3), and an emitter follower circuit (Ql, 'R4) forming an output circuit.

The inverter circuit (IN) combines the video signal formed by the parallel/serial conversion circuit (10 or 11) and the horizontal and vertical blanking signals (DISPTMG) formed by the CRT control circuit +11. input the video signal (VIDEO) and connect it to the inverter circuit (I
N, ) is a horizontal line formed by a CRT control circuit il+.
It inputs the vertical synchronization pulse (H/VSYNC).

When the above video signal (VIDEO') is "1", the output of the inverter circuit (IN) is "0", that is, the resistor (
R1) is short-circuited to form a black level signal determined by the ratio of the resistances (R, and Rt), and when it is "O", the resistance (Rt
and R,,Rs).

On the other hand, when the synchronization pulse (H/v 5YNC) is 1",
The output of the inverter circuit (IN,) is reduced to "θ", that is, the Ov level by shorting the resistors (Rt, Rs), thereby forming a synchronizing pulse level. As a result, a composite video signal as shown in FIG. 8 can be obtained.

The blanking signal (DISPTMG) forming the video signal (VIDEO) signal is used to set the CRT screen outside the display screen (24) in FIG. The direction is formed based on the output of the row counter.

In this embodiment, an inversion control circuit is provided on the output side K of the parallel/serial conversion circuit (10, 11) via the gate circuit (12) to provide a function of inverting the black and white of the display screen. be. This inverting gate circuit uses, for example, an exclusive OR circuit, and uses the -10,000 input as a control input and changes @IQZIIIIIIK to select the in-phase or anti-phase output of the video signal applied to the other input. can be obtained.

This control signal (NEG) is formed by a flip-flop circuit (16) as shown in FIG.

This flip-flop circuit (16) has, for example, 5EOA.
By assigning address 4, 'mO'' or “1”
You can control black and white reversal by writing in a program.

The video control circuit (]3) outputs a composite video signal, so it can be directly connected to a CRT for monitoring.
Although it can drive a home (permanent) TV receiver, it cannot be used as a CR.
When used as T, VHF (Very High
h Frequency) wave. The modulation circuit (14) is for this purpose, and forms a modulated signal using, for example, one channel (91, 25 MHz) or two channels (97, 25 MHz, ) in the standard television band, and transmits it from the antenna terminal. It is done manually.

In this embodiment, as shown in FIG. 1, a state detection circuit (19) is provided to detect the CRT display period. For example, this state detection circuit (19)
K, 5EOA8 address is given to determine whether or not the refresh memory (5) can be accessed from the CPU. That is, when the CPU accesses the refresh memory (5), it specifies the detection circuit (19) and
By knowing the state of the control signal (SEL) of the address selector 161, writing or the like can be executed. At this time, it is desirable for the write program to perform state detection again after executing the write command, and check whether or not writing has actually been performed by checking whether or not it is in a writable state.

data bus (DATA), address bus (ADD)
A RAM (20) and a ROM (21) are provided in the RESS to enable memory expansion of the CPU. This memory (20, 21) serves not only as a mere extension of the CPU's memory as described above, but also as a CRT display device.
Since c5) is shared for pattern display and dot display, information can be protected by using it for saving the refresh memory (5) when both are displayed alternately.

In this way, +77 retrieval memo January 5) and other memories (20, 21) are provided on the same path, and the CP
A bus driver (17) is provided in the WK to prevent information interference when exchanging information between the U and the memory (20, 21) and reading out the refresh memo (January 5) during CRT display operation at the same time. .

A bus driver (18) is necessary between the input source to the CPU and the CRT display device.

The present invention is not limited to the above-mentioned embodiments, but as long as the refresh memory (5) is a CRT display device that can be used for both pattern display and dot display, the specific structure may be changed. It doesn't matter what. Further, the number of dots constituting characters etc. can be varied in various ways, and it goes without saying that the pattern generation circuit (9) is unnecessary when no special symbol is displayed. The display mode may be switched using a manual mechanical switch or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
4 and 4 are diagrams showing the screen configuration of a CRT showing one embodiment of the present invention, FIG. 3 is a diagram explaining the operation of a pattern generation circuit showing one embodiment of the present invention, and FIG. , a specific circuit diagram of a timing controller showing one embodiment of the present invention, FIG. 6 is its operating waveform diagram, and FIG. 7 is a specific circuit diagram of a video control circuit showing one embodiment of the present invention. FIG. 8 is a diagram of its operating waveforms. il+...CRT control circuit, 121, 131...
Oscillation circuit, +41...timing controller, (
51...Refresher memory, (6)...Address selector, (7:...Address decoder, +81,
(91... pattern generation circuit, (10), (11)
... Parallel/serial conversion circuit, (12) ... Gate circuit, (13) ... Video control circuit,
(14)...Modulation circuit, (15), (16)...Frigg 70 amplifier circuit, (17), (18)...Bus driver, (19)...State detection circuit, (20) ...
RAM, (21)...ROM, (22)...CRT
, (23)...Display screen section, (24)...Display screen, (25)...1 character display screen, (27)...Character display section, (28)...Dot, ( 29), (30)・
...Branch circuit, Fig. 2 Fig. 3 Fig. 1 Dopa-to-daimi;? (VCLk:) 4th
Figure 5

Claims (1)

[Claims] 1. A CRT display having a storage area in which predetermined information corresponding to information to be displayed is stored, and in which a video signal is formed based on output information taken out from the storage area. A CRT display system, comprising a storage means for saving the storage contents of the storage area.