JPH02277382A - Pulse generation circuit - Google Patents

Abstract

PURPOSE:To prevent the shape of the leading edge of the frequency division output of a second frequency division circuit from being set differently at every cycle by offsetting the change of a current on an output buffer by the influence of the frequency division output of the second frequency division circuit different at every cycle in which the change of the current on the output buffer is affected on the frequency division output of the second frequency division circuit. CONSTITUTION:The influence different at every cycle of the pulse of 8/5fsc of the second frequency division circuit 6 in which the change of the current on the output buffer 3 by a pulse of 4fsc outputted from a first frequency division circuit 2 is affected on the pulse of 8/5fsc outputted from the second frequency division circuit 6 is offset by the influence different at every cycle of 8/5fsc of the second frequency division circuit 6 in which the change of the current on the output buffer 5 by the output of a phase inversion circuit 4 having a phase difference (pi) for the pulse of 4fsc of the first frequency division circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a pulse generation circuit that generates horizontal transfer pulses for driving a solid-state image sensing element in, for example, a solid-state image sensing device.

[Conventional technology]

Nowadays, imaging devices using solid-state imaging devices are rapidly becoming popular, and further improvement in image quality is desired, and development thereof is actively underway.

A conventional solid-state imaging device will be described below with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of the solid-state imaging device.

In FIG. 3, 24 is a solid-state image sensor composed of a CCD element or the like. 21 is a pulse generation circuit that generates a mask clock [for example, a signal with a frequency four times the color subcarrier (frequency fsc) (hereinafter abbreviated as 4fsc)] and a horizontal transfer pulse φH for driving the solid-state image sensor 24. and vertical transfer pulse φ■. 22 is a synchronization signal generation circuit, and 4f output from the pulse generation circuit 21;
.

horizontal drive signal HD, based on the master clock of
Vertical drive signal VD and other synchronization signals, etc.
Generates pulses necessary for signal processing.

23 is a drive circuit which generates the horizontal transfer pulse φ[I and the vertical transfer pulse φV output from the pulse generation circuit 21.
is converted into a voltage level necessary to drive the solid-state image sensor 24, and applied to the solid-state image sensor 24 as a horizontal transfer drive pulse φH' and a vertical transfer drive pulse φV'.

Here, the pulse generation circuit 21 for driving the horizontal 3001 (and vertical 240) solid-state image sensor 24 will be specifically explained with reference to FIG.

First, in oscillator 1, a frequency (8 times higher than the color subcarrier) (
(hereinafter abbreviated as 8fsc), this 8fs pulse is generated.
The pulse of c is input to a first frequency divider circuit 2 that divides the frequency by 2 and a second frequency divider circuit 6 that divides the frequency by 5. 8f mentioned above
The pulse waveform of sc is shown in FIG. 5(a).

The 4 fsc pulse, that is, the mask clock, output from the first frequency dividing circuit 2 is sent from the output terminal 9 to the synchronizing signal generating circuit 22 through the output sofa 3. The synchronizing signal generating circuit 22 generates a horizontal drive signal ) 1 and a vertical drive signal VD based on the mask clock and supplies them to the pulse generating circuit 21 . This 4fsc pulse waveform is shown in FIG. 5(b).

On the other hand, (815) fS output from the second frequency dividing circuit 6
The pulse C is input to a waveform shaping circuit, Zunawara horizontal transfer pulse generation logic circuit 7, and this horizontal transfer pulse generation logic circuit 7 generates a horizontal transfer pulse φH.
Drive circuit 2 from output terminal 11 through output cover and F8
Sent to 3. The second frequency dividing circuit 6 outputs (
815) The pulse waveform of f sc is shown in FIG. 5 (C1).

Note that the generation circuit for the vertical transfer pulse φ■ is not directly related to the present invention, and is therefore not shown.

[Problem to be solved by the invention]

However, in the configuration shown in FIG. 4 as described above, as can be seen from FIGS. 5(b) and (C), (815) E
The edges of the 4fsc pulse that fall on the rising edge of the SC pulse alternate with rising and falling edges. Therefore, the rising edge of the (815) fsc pulse is affected by the change in the current flowing through the output sofa 3 of the 4fsc pulse, and as shown in FIG.
As shown by the broken line in C1, the shape changes every cycle.

As a result, this also affects the horizontal transfer pulse φH generated by the horizontal transfer pulse generation logic circuit 7 based on the pulse of (815) fsc, and this horizontal transfer pulse φ
The rising edge of H is shown in Figure 5 (C1 (8)
15) fs. It is similar to the pulse of When the solid-state image sensor 24 is driven by this horizontal transfer pulse φH, vertical stripes are generated in the image captured by the solid-state image sensor 24 in the horizontal direction, each bit being different in brightness and darkness.

Therefore, an object of the present invention is that the edge of the divided output of the first frequency dividing circuit that appears at the same timing as the rising edge of the divided output of the second frequency dividing circuit is the same as the rising edge of the divided output of the second frequency dividing circuit. The shape of the rising edge of the divided output of the second frequency dividing circuit differs every period of the divided output of the second frequency dividing circuit due to the switching between rising and falling every one cycle of . An object of the present invention is to provide a pulse generation circuit that can prevent the above problems.

[Means to solve the problem]

The pulse generating circuit of the present invention has a frequency f of each divided output of the first and second frequency dividing circuits that divide the output signal of the oscillator.
1, f2 = 2 f+ when n is an integer
/(1+2n) In this pulse generator, a frequency division ratio is set to satisfy the relationship, and a phase inversion circuit is provided to invert the phase of the frequency division output of the first frequency division circuit.

[For production]

According to the configuration of the present invention, the change in the current flowing to the output Hanofa due to the frequency division output of the first frequency division circuit does not reach the frequency division output of the second frequency division circuit, and the frequency division output of the second frequency division circuit The shadow that varies every cycle is because the change in the current flowing to the output sofa due to the output of the phase inversion circuit does not affect the divided output of the second frequency dividing circuit, and the difference occurs during one cycle of the divided output of the second frequency dividing circuit. just offset by different influences. In other words, the influence of the divided output of the first frequency dividing circuit and the output of the phase inversion circuit on the divided output of the second frequency dividing circuit is the same as the frequency multiplied by the frequency divided output of the second frequency dividing circuit. Become. As a result, when a horizontal transfer pulse for driving a solid-state image sensor is generated based on the frequency-divided output of the second frequency divider circuit, this horizontal transfer pulse is also uniform for all bits, and the solid-state image sensor This prevents the occurrence of vertical stripes in images taken with .

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a circuit diagram of a pulse generating circuit 21' for a solid-state image pickup device of 300H horizontally and 240V vertically in an embodiment of the present invention. This pulse generating circuit 21' is used in place of the pulse generating circuit 21 in the solid-state imaging device shown in FIG.

First, in the oscillator 1, a pulse of 8 fsc is generated in the same way as in FIG.
and a second frequency dividing circuit 6 that divides the frequency by 5, respectively. The above 8fsc pulse waveform is converted to the 21st Fsc.
(shown in al.

The 4 fsc pulse, that is, the mask clock, output from the first frequency dividing circuit 2 is sent to the synchronizing signal generating circuit 22 through the output panopher 3 through the output terminal 9, as in FIG. The synchronization signal generation circuit 22 generates a horizontal drive signal HD and a vertical drive signal V based on the mask clock.
D is generated and applied to the pulse generation circuit 21. This 4fs
The pulse waveform of c is shown in Fig. 2 (bl).

Furthermore, although the following parts are not shown in FIG. 4 and are the main parts of the present invention, the 4 output from the first frequency dividing circuit 2
The fsc pulse is passed through a phase inversion circuit 4 consisting of impark etc.
, the phase of the 4fsc pulse is inverted from the phase inversion circuit 4, that is, a pulse of ``rπ'' having a phase difference π is output and sent to the output terminal 10 through the output sofa 5.This 4fsc pulse The second waveform
Shown in Figure FC+.

On the other hand, (815) rs output from the second frequency dividing circuit 6
Similarly to FIG. 4, the pulse c is inputted to the horizontal transfer pulse generation logic circuit 7 which is a waveform shaping circuit, and the horizontal transfer pulse generation logic circuit 7 converts it into a horizontal transfer pulse φH.
is generated and sent from the output terminal 11 to the drive circuit 23 through the output sofa 8. The pulse waveform of fSC (815) outputted from the second frequency dividing circuit 6 is shown in FIG. 2 +dl.

In the pulse generation circuit configured as described above, the pulse generation circuit shown in Fig. 2 (
The 4fsc pulse of bl and the 4f5.bl pulse of FIG. 2(C). Since the phase difference between the pulses is π, the sum of the current flowing through the output sofa 3 of the 4 fsc pulse and the current flowing through the output sofa 5 of the 4 fsc pulse is always constant at the edge. That is, the change in the current flowing through the output sofa 3 due to the 4fsc pulse output from the first frequency divider circuit 2 is output from the second frequency divider circuit 6 (815).
(8
15) One round of f sc pulse! For each U1, the output of the phase inverting circuit 4 having a phase difference π with respect to the 4 fsc pulse of the first frequency dividing circuit 2, that is, 4 fs
The change in the current flowing through the output sofa 5 due to the pulse of c does not reach the pulse of (815) fsc of the second frequency dividing circuit 6, and the change in the current flowing through the output sofa 5 due to the pulse of (815) fsc of the second frequency dividing circuit 6 changes every cycle of the pulse of (815) just offset by different influences. Therefore, 4f for the rising edge of the (815) fsc pulse, which has been a problem in conventional pulse generation circuits.

The influence of the pulse of (815) becomes uniform for the double period of the pulse of rsc. As a result, based on the (815) f sc pulse of the second frequency dividing circuit 6, a horizontal transfer pulse φ11 for driving the solid-state image sensor 24 is generated, for example.
is generated, this horizontal transfer pulse φII is also uniform for all bits, making it possible to prevent the occurrence of vertical stripes in the image captured by the solid-state imaging device 24, and improving the image quality of the pixels captured by the solid-state imaging device 24. can be significantly improved.

In the above embodiment, the first frequency dividing circuit 2 outputs a pulse of 4 fsc, and the second frequency dividing circuit 6 outputs a pulse of (815) fsc.
Therefore, the relationship between the frequency f of the divided output of the first frequency dividing circuit and the frequency f2 of the divided output of the second frequency dividing circuit is n = 2, and fz = 2. f+15, but even if n is an integer other than 2, the frequency f1
, f2 have the relationship expressed by fz = 2 f+ / (1+2n), this invention can be applied.

〔Effect of the invention〕

According to the pulse generating circuit of the present invention, since the phase inverting circuit for inverting the phase of the frequency division output of the first frequency division circuit is provided, the current flowing to the output sofa due to the frequency division output of the first frequency division circuit and the phase The influence of the output of the inverting circuit on the divided output of the second frequency dividing circuit by the current flowing to the output cover sofa can be made the same at twice the frequency of the divided output of the second frequency dividing circuit.

As a result, the edge of the divided output of the first frequency dividing circuit, which appears at the same timing as the rising edge of the divided output of the second frequency dividing circuit, changes every period of the divided output of the second frequency dividing circuit. By switching between rising and falling edges, it is possible to prevent the shape of the rising edge of the frequency-divided output of the second frequency-dividing circuit from being different for each cycle of the frequency-divided output of the second frequency-dividing circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a pulse generation circuit according to an embodiment of the present invention, FIG. 2 is a time chart of each part of FIG. 1, and FIG. 3 is a block diagram showing an example of the configuration of a conventional solid-state imaging device. 4 is a block diagram showing an example of the configuration of a conventional pulse generating circuit, and FIG. 5 is a time chart of each part of FIG. 4. DESCRIPTION OF SYMBOLS 1... Oscillator, 2... First frequency dividing circuit, 3... Output cover sofa, 4... Phase inversion circuit, 5... Output cover,
F, 6...Second frequency dividing circuit, 7...Horizontal transfer pulse generation logic circuit book

Claims (1)

[Claims] Frequencies f_1 and f_2 of the divided outputs of the first and second frequency dividing circuits that divide the output signal of the oscillator have the relationship of f_2=2f_1/(1+2n), where n is an integer. A pulse generation circuit in which a frequency division ratio is set to satisfy the following conditions, further comprising a phase inversion circuit that inverts the phase of the frequency division output of the first frequency division circuit.