JPH0227762U - - Google Patents
Info
- Publication number
- JPH0227762U JPH0227762U JP10593788U JP10593788U JPH0227762U JP H0227762 U JPH0227762 U JP H0227762U JP 10593788 U JP10593788 U JP 10593788U JP 10593788 U JP10593788 U JP 10593788U JP H0227762 U JPH0227762 U JP H0227762U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- multilayer
- view
- electrically
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Combinations Of Printed Boards (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
第1図は本考案の一実施例の混成集積回路モジ
ユールの概略斜視図、第2図はその縦断面図、第
3図はこの実施例における部品の多層混成集積回
路基板の接続装置を示す斜視図、第4図、第5図
、第6図はその他のそれぞれ別の接続装置を示す
斜視図、第7図はこれらの実施例の多層集積回路
基板にリードを取付けた状態を示す図、第8図は
その他のリード取付状態を示す図である。
図中、11,12,13,14は多層混成集積
回路基板、14b,14b……,15,15……
は電子部品、16はクリツプ、17は導電性接続
体、18はセラミツクチツプ、19,19は接続
ピンである。
FIG. 1 is a schematic perspective view of a hybrid integrated circuit module according to an embodiment of the present invention, FIG. 2 is a vertical sectional view thereof, and FIG. 3 is a perspective view showing a connecting device of a multilayer hybrid integrated circuit board of components in this embodiment. 4, 5, and 6 are perspective views showing other connection devices, and FIG. 7 is a view showing the state in which leads are attached to the multilayer integrated circuit board of these embodiments. FIG. 8 is a diagram showing another lead attachment state. In the figure, 11, 12, 13, 14 are multilayer hybrid integrated circuit boards, 14b, 14b..., 15, 15...
16 is an electronic component, 16 is a clip, 17 is a conductive connector, 18 is a ceramic chip, and 19, 19 are connection pins.
Claims (1)
る多層混成集積回路基板をその両面に電子部品搭
載可能に複数枚垂直方向に並べ、かつ電気的及び
機械的に結合したことを特徴とする混成集積回路
モジユール。 A hybrid integrated circuit characterized in that a plurality of multilayer hybrid integrated circuit boards each consisting of a plurality of laminated layers forming a hybrid integrated circuit are arranged vertically so that electronic components can be mounted on both sides thereof, and are electrically and mechanically coupled. circuit module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10593788U JPH0227762U (en) | 1988-08-12 | 1988-08-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10593788U JPH0227762U (en) | 1988-08-12 | 1988-08-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0227762U true JPH0227762U (en) | 1990-02-22 |
Family
ID=31338999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10593788U Pending JPH0227762U (en) | 1988-08-12 | 1988-08-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0227762U (en) |
-
1988
- 1988-08-12 JP JP10593788U patent/JPH0227762U/ja active Pending
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