JPH0227770A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To employ a second silicon oxide film as a mask for impurity ion implanting to form source, drain regions by forming the oxide film on a channel forming region. CONSTITUTION:After a silicon nitride film 107 is formed on a first silicon oxide film 106, resist is formed on a region except a channel forming region 108, and the film 107 is removed with thermal phosphoric acid. Then, a polycrystalline silicon film 103 is thermally oxidized to form a second silicon oxide film 109. In this case, it is so thermally oxidized to allow the film 103 to become the region 109 to remain. Thus, the film 109 can be employed as a mask for impurity ion implanting to form a source region 104 and a drain region 105.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a MOS type silicon thin film transistor of a semiconductor device.

[Prior Art 1] As the degree of integration of LSIs increases, MOS type silicon thin film transistors are becoming more and more important.

A conventional method for manufacturing a MOS type silicon thin film transistor of a semiconductor device is as shown in FIGS. 2(a) to 2(e). This will be explained step by step.

First, as shown in FIG. 2(a), a first silicon oxide film 202 is deposited as an insulating film on a substrate 201 by chemical vapor deposition.
form angstroms. Then, a first silicon layer 203 is formed on the first silicon oxide film 202 by a 2000 Å Rohm chemical vapor deposition method.

Next, as shown in FIG. 2(b), a resist 205 is formed on the first silicon film 203 which will be used as a channel forming region 204, and an impurity such as arsenic is implanted to form a source region 206 and a drain region 207.

Next, as shown in FIG. 2(C), the resist 205 is removed. Unnecessary portions of the first silicon MM 203 are removed by a photo-etching process. Then, gate oxide 111208 is formed by thermal oxidation in an oxygen atmosphere.

Next, as shown in FIG. 2(d), a second silicon layer 209 having a thickness of 2000 angstroms is formed on the gate oxide film 208. Then, second impurity implantation 211 is performed.

Next, as shown in FIG. 2(e), the second silicon 11!2
A gate electrode 212 is formed by photo-etching so as to leave a necessary portion of 09. Then, heat treatment is performed at 900'C for 20 minutes to activate impurities. After that, the drawer arrangement 49213 was formed.

(Problems to be Solved by the Invention) MOS type silicon thin film transistors have disadvantages such as a larger leakage current between the source and drain regions and a lower 0Nil current compared to single crystal transistors. One way to improve this is to make the silicon film thinner.

A recent example is “High Performance”
e S01MO5FET Using Ultra
a-thin SOI Film: Toshi
ba VLSI Research Center: 6
40-IEDM 87.

In order to reduce the leakage current between the source and drain regions and to increase the 0NiJ current, it is sufficient to reduce the thickness of the silicon film. At the same time, since it becomes thinner, the resistance value of the source and drain regions increases, which is a problem. Further, to form the source and drain regions, impurities such as arsenic, phosphorus, and boron are implanted, that is, ion-implanted. At this time, if the silicon film is thin, impurities will penetrate the silicon film, and as a result, the resistance value will not decrease and may affect other elements below.

Therefore, with the above-mentioned conventional technology, it is difficult to create a MOS type silicon thin film transistor that has source and drain regions with low resistance values, low leakage current between the source and train regions, and high ON current. It has the problem that. The present invention is intended to solve these problems, and aims to have source and drain regions with a low resistance value, have a small leakage current between the source and drain regions, and have a low ON current. is high and does not affect the elements of the pond.
The present invention provides a method for manufacturing a MOS type silicon thin film transistor.

[Means for Solving the Problems] The semiconductor device of the present invention includes (1) a MOS type silicon thin film transistor formed on a substrate with an insulating film interposed therebetween, including the steps of: a) forming a silicon thin film on the insulating film; , b) Baking the silicon nitride film on areas other than the channel forming region; C) thermally oxidizing the silicon nitride film so that the channel forming region remains; d) removing the silicon nitride film; e) by the thermal oxidation. a step of implanting impurities using the formed oxide film as a mask; f) a step of removing the oxide film.

g) a step of forming a gate film; and h) a step of forming a gate electrode.

[Embodiment 1] FIGS. 1(a) to 1(g) are main sectional views of each manufacturing process of a semiconductor device in one embodiment of the present invention. The details will be explained step by step below.

First, as shown in FIG. 1(a), an insulating film 102 with a thickness of 1000 angstroms is formed on a semiconductor substrate 101 to isolate it from other elements6.
The polycrystalline silicon film 103 is deposited by thermally decomposing the normal monosilane gas forming the polycrystalline silicon film 103 at 620°C. The thickness of the polycrystalline silicon film 103 is the same as that of the source region 104 and the drain region 105, and when impurity ions are implanted to form the source region 104 and the drain region 105, the impurity is A film thickness that does not penetrate the polycrystalline silicon film 103, that is, 25
The thickness should be 0.00 angstroms or more.

Note that amorphous silicon deposited at 560° C. may also be used, and the polycrystalline silicon film 1 may be deposited in a thermal oxidation furnace.
03 is thermally oxidized in an oxygen atmosphere to form a first silicon oxide film 106 having a thickness of 200 angstroms. Then, a silicon nitride film 107 is deposited on λ by chemical vapor deposition.
After forming the angstrom, the channel forming region 108
A resist is formed in areas other than those to be removed, and the silicon nitride film 107 is removed using hot phosphoric acid.

Next, as shown in FIG. 1(b), the polycrystalline silicon l1i103 is thermally oxidized in an oxygen atmosphere in a thermal oxidation furnace.
A silicon oxide film 109 is formed. At this time, the polycrystalline silicon III which becomes the channel forming region 108
Thermal oxidation is performed to leave 03.

The thickness of the second silicon oxide film 109 is set to be at least 2000 angstroms, which is a thickness that impurities do not penetrate when implanting impurity ions to form the source region 104 and the drain region 105. .

Next, as shown in FIG. 1(c), the nitride 111107 is removed with hot phosphoric acid, and impurity ions such as phosphorus or boron are implanted to form the source region 104 and the drain region 105. Drive DOSE II 6X10”6012 or more so that the resistance value is sufficiently lowered.

Next, as shown in FIG. 1(d), the first silicon oxide film 1
06 and the second silicon oxide 111109 are removed by immersion in a hydrofluoric acid aqueous solution. Then, unnecessary portions of the first polycrystalline silicon film 103 are removed by a photo-etching process.

Next, as shown in FIG. 1(e), thermal oxidation is performed in an oxygen atmosphere at 900° C. to form a gate oxide film 111 with a thickness of 500 angstroms. Next, to form a gate electrode 112, a second polycrystalline silicon film 113 having a thickness of 2000 angstroms is formed on the gate oxide 1[1111]. In order to lower the resistance of the second polycrystalline silicon film 113,
Second impurity ions such as phosphorus or boron are implanted.

DOSEj16X 10”c so that the resistance value is sufficiently low
Input more than m-”.

Next, as shown in FIG. 1(f), the second polycrystalline silicon 1
The gate electrode 112 is formed by photo-etching so as to leave a necessary portion of 1113, and then heat treatment is performed at 900° C. for 40 minutes in a nitrogen atmosphere to activate the impurities.

Next, as shown in FIG. 1(g), a second insulating film 114 is formed to isolate it from other elements. 100 by chemical vapor deposition method
Formed with a thickness of 0 angstrom or more. Thereafter, contact holes are formed in the second insulating film 114 by a photo-etching process in order to connect to other elements. Then, by sputtering aluminum and removing unnecessary parts through a photo-etching process,
Form l5.

Through the above steps, the MOS type silicon thin film transistor of the present invention is completed.

M of an embodiment of the present invention completed through the above-mentioned steps
The OS type silicon thin film transistor has the second silicon oxide film 10 on the channel forming region 108, respectively.
By forming 9.

The source region 104 and the drain region 1
It has the advantage that it can be used as a mask for impurity ion implantation to form 05. Further, when the length of the channel forming region 108 is shortened and used for miniaturization, the channel forming region 108 has the following characteristics:
Such an electric field extends the depletion layer and causes bunch-through. However, in the embodiments described above, at both ends of the second silicon oxide film 109 on the source region 104 and the drain region 105, an overhang toward the source region 104 and the drain region 105 called a bird's beak occurs. Impurity ions are implanted into the boundaries between the channel forming region 108, the source region 104, and the drain region 105 through the bird's beak, so that the impurity concentration is reduced. Therefore, the source region 104 and the drain region 10
The electric field strength applied to 5 is reduced, making it difficult for the depletion layer to extend. That is, punch-through is less likely to occur, the length of the channel forming region 108 can be further shortened, and miniaturization is possible accordingly. Furthermore, by reducing the electric field strength, hot carrier effects are reduced and reliability is improved.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various changes can be made without departing from the gist thereof.

〔Effect of the invention〕

As described above, according to the invention, the following effects can be obtained in a MOS type silicon thin film transistor.

(1) Since the source region and the drain region are thicker than the channel forming region, it is possible to produce a MOS type silicon thin film transistor in which the leakage current between the source region and the train region is small and the ON current is high.

(2) It is possible to create a highly reliable MO8 type silicon thin film transistor that does not affect the underlying elements for a long time.

(3) It is possible to create a MOS type silicon thin film transistor that can be miniaturized and can be highly integrated.

(4) Since the resistance values of the source region and drain region are low, it is possible to create a MOS type silicon thin film transistor that can operate at high speed.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(g) are main sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 2(a) to 2(e) are main cross-sectional views showing a conventional method of manufacturing a semiconductor device. 101... Semiconductor substrate 102... Insulating film 103 ・ 104 ・ 105 ・ 106 ・ 107 ・ 108 ・ 109 ・ 110 ・ 111 ・ 112 ・ 113 ・ 114 ・ 115 ・ 201 ・ 202 ・ 203 ・ 204 ・ 205 ・ 2 06 ・207 - Polycrystalline silicon film, source region, drain region, first silicon oxide film, silicon nitride, channel formation region, second silicon oxide film, impurity ion beam, gate oxide film, gate electrode, second polycrystalline silicon Film, second insulating film, wiring, substrate, first silicon oxide film, first silicon film, channel formation region, resist, source region, drain region, gate oxide film, second silicon film, second impurity implantation, gate electrode・Wiring/Second insulating film and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Masatoshi Kamiyanagi (and 1 other person) Ne (Mo) Kamo λ Kuchi (C) Ueri Tomoe

Claims (1)

[Claims] (1) In a MOS silicon thin film transistor formed on a substrate via an insulating film, a) forming a silicon thin film on the insulating film, b) patterning the silicon nitride film in areas other than the channel formation region. c) thermally oxidizing so that the channel forming region remains; d) removing the silicon nitride film; e) implanting impurities using the oxide film formed by the thermal oxidation as a mask; A method for manufacturing a semiconductor device, comprising:) removing the oxide film; g) forming a gate film; and h) forming a gate electrode.